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Surface Code Error Correction Patents: Who Leads, Gaps 2026

Surface Code Error Correction Patents: Who Leads, Gaps 2026
https://www.patsnap.com/resources/blog/rd-blog/surface-code-error-correction-hardware-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Quantum Technology · Patent Landscape
Surface code error correction hardware patents: mapping who holds the qubit-grid claims
  • One assignee dominates the record. Google LLC holds 16 of the records in the ranked set, against single-digit or single-record counts for every other listed applicant.
  • Filing peaked in 2017, then went quiet. The trend runs 9 filings in 2017 down to 0 at the 2022 midpoint before a small recent uptick — publication lag means the last year or two is always understated.
  • Every record touches AI-based computing classes. All 17 records in scope carry a G06N classification, with just over half also tagged H03K for pulse and logic-circuit technique — a narrow technical corridor.
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17
Published Records
US
Leading Jurisdiction
7
Active Filers Ranked
2017
Peak Filing Year

Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Field Overview

What this landscape covers

Surface code error correction hardware sits at the intersection of qubit-grid engineering and classical control logic: the syndrome-extraction cycles, decoder latency budgets and real-time feedback paths that turn noisy physical qubits into a usable logical qubit. This dataset tracks 17 published records filed or published between 2015 and 2026 whose title or claims name surface code error detection, quantum error correction thresholds, or logical qubit demonstrations, and whose claims or description reference syndrome extraction, decoder latency, real-time feedback, correlated error handling, leakage handling or scaling.

The scope is deliberately narrow: it is not general quantum computing hardware, but the specific control and correction layer that sits between a physical qubit array and a fault-tolerant logical qubit. That narrowness is visible in the assignee list and the classification spread below, both of which point to a field still concentrated around one early mover.

Filing activity, 2015-2026
  1. 1Google LLC16
  2. 2MR SATHISH KRISHNA ANUMULA1
  3. 3DR Y SARITHA KUMARI1
  4. 4DR V P GEETHA VANI1
  5. 5DR SAMUEL TALARI1
  6. 6DR R NITHYA1
  7. 7DR C C SANGEETHA1
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
The Numbers

Filing trend and technology composition

Two views of the same 17 records: how filing activity moved year over year, and which IPC subclasses the claims actually sit in.

A 2017 peak, a quiet middle, and a small recent tick

Filings ran at 9 in 2017, the peak so far, then fell toward the 2022 midpoint where the trend records 0. A small recent uptick follows, but because publication typically lags filing by around 18 months, the most recent year or two in this trend understates actual filing activity and should not be read as the field cooling for good.

A 2017 peak, a quiet middle, and a small recent tick035810920172018201920202021202220232024202512026Most recent year is partial — publication lag means later filings are not yet visible.

Concentrated in AI-adjacent computing and pulse logic

All 17 records in scope carry a G06N classification (computing arrangements based on specific computational models), making it the near-universal tag for this search. H03K (pulse technique and logic circuits) appears on 9 records, 52.9% of the 17, reflecting the real-time feedback and decoder-timing claims at the hardware-control layer. H10N (other electric solid-state devices) appears on just 1 record, 5.9% of the 17 — a thin footprint given how central physical qubit fabrication is to the field.

Concentrated in AI-adjacent computing and pulse logicG06N · Computing based on AI models17100.0%H03K · Pulse technique & logic circui…952.9%H10N · Other electric solid-state dev…15.9%

Shares are the percentage of the 17 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.

Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.

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Key Patents

The most-cited records in this set

Representative Record
US20210035006A12021-02-04

Reducing parasitic interactions in a qubit grid for surface code error correction

GOOGLE LLC

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, perpendicular to the first, with the second direction opposite the third.US20210035006A1 · Google LLC · published 2021-02-04

US20210035006A1 — patent drawing 1US20210035006A1 — patent drawing 2
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Highest-citation records
#Publication no.Patent titleCitations
1WO2019032103A1Reducing parasitic interactions in a qubit grid for surface code error correction14
2US20210035006A1Reducing parasitic interactions in a qubit grid for surface code error correction11
3US11562280B2Reducing parasitic interactions in a qubit grid for surface code error correction10
4US20240378473A1Reducing parasitic interactions in a qubit grid for surface code error correction2
5US12056575B2Reducing parasitic interactions in a qubit grid for surface code error correction2
6US12536463B2Reducing parasitic interactions in a qubit grid for surface code error correction1
7US20240062086A1Reducing parasitic interactions in a qubit grid for surface code error correction1
8US11763186B2Reducing parasitic interactions in a qubit grid for surface code error correction1

Citation counts inside a searched corpus favour older filings — treat these as a signal of influence on later filers, not a ranking of current technical importance.

Publication numbers are shown where the record carries one (8 of 8 rows); clicking a row searches Eureka by that number.

Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Insights

What the data means for a filing decision

Three findings that shape where a new application would actually land relative to existing claims.

Concentration
16 of the ranked set
Google LLC filings

One applicant set the claim baseline

The leading assignee accounts for 16 records against a fifth-place count of 1 across the seven ranked companies. New filings in the qubit-grid parasitic-interaction space should assume Google's published claims as the prior art to design around first.

Assignee ranking, 7 companies
Timing
9 filings in 2017
peak year

The trend peaked early and dipped through the midpoint

Filing activity peaked at 9 in 2017 and fell to 0 by the 2022 midpoint. A small recent tick is visible, but with publication lagging filing by roughly 18 months, the last one to two years understate real activity rather than showing a field in decline.

Filing trend, 2015-2026
Classification
100% G06N
of 17 records

Claims sit almost entirely in AI-model computing classes

Every record in scope carries a G06N tag, with H03K pulse-and-logic-circuit claims on just over half. H10N solid-state device claims — the physical qubit fabrication layer — appear on only 1 record, a narrow footprint relative to how central fabrication is to scaling error correction hardware.

IPC composition, 17 records
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Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to surface code error correction hardware, with the prior art for and against each one.

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Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Players

Who is filing, and where the field is still open

The ranked set is short — seven companies — and dominated by one filer, with a cluster of individually-named applicants each holding a single co-filed record.

Leader
16 records
of the ranked set

Google LLC

Google holds the large majority of records in this ranking, including the most-cited documents in the set, all centred on reducing parasitic interactions in a qubit grid during surface code error detection cycles.

Recent-year momentum: 1 filing in the latest year
Long tail
1 record each
fifth place and below

Individually-named co-filers

Below the leader, the ranking drops to single-digit and single-record counts held by individually named applicants who appear together across 10 co-assignee pairs, suggesting small collaborative filing groups rather than competing corporate labs.

10 co-assignee pairs recorded
Momentum
-100% YoY
for four of the six tracked assignees

Most non-leading filers went quiet in the latest year

Four of the six assignees with recent-year momentum data show a full year-over-year drop to zero filings, while the leader still recorded 1 filing in the latest year — a gap that widens the leader's relative position even as overall volume stays low.

Momentum by assignee, latest year
🔍
Under-claimed branches worth checking before filing
Sub-areas where the classification and citation data show thin coverage relative to the field's technical scope.
Leakage handling at the physical qubit layerCorrelated-error mitigation across syndrome cyclesDecoder latency budgeting in real-time feedback loopsSolid-state qubit fabrication for scaled grids
Rank all filers by momentum →
Filing momentum by assignee
AssigneeRecent yearYoY
Google LLC1
MR SATHISH KRISHNA ANUMULA0-100%
DR Y SARITHA KUMARI0-100%
DR V P GEETHA VANI0-100%
DR SAMUEL TALARI0-100%
DR R NITHYA0-100%
DR C C SANGEETHA0-100%
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's Next

Where to take this from here

The published record set is small and concentrated — the next step is usually a claim-level read of the leading filer's family, followed by a check of the thinner classification branches.

Read the leading filer's claim scope

Start with the most-cited records tied to the qubit-grid parasitic-interaction work and map exactly which method steps and hardware arrangements are claimed versus merely described.

Open the family in Eureka

Check the thin H10N branch for openings

With only 1 of 17 records tagged to solid-state device claims, a fabrication-focused filing may face less occupied claim space than a control-logic filing would.

Explore IPC H10N records in Eureka
Source: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ

Common questions on this landscape

Answers are grounded in the same dataset. Derived from a Patsnap search on Surface Code Error Correction Hardware covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.

Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.

Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.

Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.

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