pSemi Corp. vs. Cirrus Logic: Dismissed With Prejudice in Semiconductor Patent Dispute
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📋 Résumé de l'affaire
| Nom de l'affaire | pSemi Corp. v. Cirrus Logic, Inc. |
| Numéro de dossier | 1:25-cv-00415 (D. Del.) |
| Tribunal | Tribunal fédéral de première instance pour le district du Delaware |
| Durée | Apr 2025 – Feb 2026 307 days |
| Résultat | Rejeté avec préjudice |
| Brevets en cause | |
| Produits incriminés | Cirrus Logic LN8411 Product Line |
Aperçu du dossier
In a case that underscores the high-stakes nature of semiconductor intellectual property disputes, pSemi Corp.’s patent infringement action against Cirrus Logic, Inc. concluded with a stipulated dismissal with prejudice on February 3, 2026—just 307 days after filing. Case No. 1:25-cv-00415, heard before Judge Gregory B. Williams in the United States District Court for the District of Delaware, involved three U.S. semiconductor patents and targeted Cirrus Logic’s LN8411 product line.
The outcome—a mutual dismissal with each party bearing its own attorneys’ fees and costs—offers no public admission of liability or wrongdoing by either side. Yet the resolution carries meaningful implications for semiconductor patent litigation strategy, freedom-to-operate (FTO) analysis, and the evolving dynamics between fabless semiconductor IP holders and integrated circuit developers. For patent attorneys, IP professionals, and R&D teams operating in the power management and analog semiconductor space, this case provides a valuable data point on assertion strategy, venue selection, and negotiated resolution timelines.
Les parties
⚖️ Demandeur
A wholly owned subsidiary of Murata Manufacturing Co., Ltd., specializing in RF and power management integrated circuits with a robust patent portfolio.
🛡️ Défendeur
A fabless semiconductor company known for high-precision analog and mixed-signal integrated circuits, serving audio, power conversion, and consumer electronics markets.
Brevets en cause
This litigation involved three recently issued U.S. patents in the semiconductor technology domain. Their high publication numbers indicate issuance within the 2024–2025 timeframe, reflecting pSemi’s active prosecution strategy in rapidly evolving semiconductor design areas.
- • US12212232B2 — Semiconductor architecture for power management ICs
- • US12143010B2 — High-efficiency power conversion methodologies
- • US12113438B2 — Integrated circuit design for analog and mixed-signal applications
Developing a new power management IC?
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Le verdict et l'analyse juridique
Résultat
The case was resolved via stipulated dismissal with prejudice, jointly submitted by counsel from Quinn Emanuel and Morris Nichols. The order states: “All claims asserted in this case shall be dismissed with prejudice, with each party to bear its own attorneys’ fees, expenses, and costs.” No damages award, injunctive relief, or licensing terms were publicly disclosed. The “with prejudice” designation means pSemi cannot re-file the same claims against Cirrus Logic based on the same patents and same accused conduct.
Principales questions juridiques
The case was initiated as a standard patent infringement action. Because the matter resolved by stipulation before trial or dispositive motion rulings, no judicial findings on infringement, validity, claim construction, or damages were issued. This means the case sets no binding legal precedent. The absence of a licensing disclosure, combined with each party bearing its own costs, suggests a confidential resolution, such as a cross-license, a design-around by Cirrus Logic, or a commercial negotiation.
Points stratégiques à retenir
This case reveals important insights into assertion strategy and resolution dynamics for recently issued semiconductor patents. The filing of suit based on patents issued within 12–18 months of the application’s progression through prosecution represents an increasingly common “fast-assertion” strategy, leveraging newly granted claims against concurrent competitive products.
For patent holders, asserting recently issued patents with claim mapping tied to specific competitor schematics demonstrates thorough pre-litigation preparation. For accused infringers, retaining experienced patent defense counsel early positions them favorably for both litigation and negotiation. The mutual cost-bearing structure suggests neither party achieved a clearly superior public outcome, reflecting balanced litigation posture.
Analyse de la liberté d'exploitation (FTO)
This case highlights critical IP risks in semiconductor design. Choose your next step:
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- View all 80+ related patents in the power management IC space
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Zone à haut risque
Power management ICs & analog circuits
80+ Related Patents
In power management IC space
Options de contournement
Disponible pour la plupart des réclamations
✅ Points clés à retenir
Stipulated dismissals with prejudice in Delaware semiconductor cases frequently reflect confidential licensing resolutions—monitor subsequent SEC filings.
Rechercher la jurisprudence connexe →The absence of claim construction or invalidity rulings limits precedential value but preserves both parties’ IP positions for future assertions.
Explorer les précédents →Annotated schematics as litigation exhibits confirm that product-level technical detail is central to infringement mapping—maintain rigorous design documentation.
Lancer l'analyse FTO pour mon produit →Conduct FTO analyses against pending patent applications, not only issued patents, especially from portfolio-intensive companies like pSemi/Murata.
Essayer la rédaction de brevets par IA →Foire aux questions
Three U.S. patents were asserted: US12212232B2, US12143010B2, and US12113438B2, all in the semiconductor technology domain, specifically relating to power management integrated circuits.
The case was dismissed with prejudice by stipulation on February 3, 2026, with each party bearing its own fees and costs. No damages or injunctive relief were publicly awarded, suggesting a confidential settlement or strategic withdrawal.
It reinforces that recently issued, claim-mapped semiconductor patents can generate swift resolutions—whether through licensing or strategic withdrawal—without requiring full trial proceedings. It highlights the importance of fast-assertion strategies for patent holders.
R&D teams in the semiconductor industry should maintain rigorous design documentation and conduct Freedom-to-Operate (FTO) analyses not only against issued patents but also against pending applications, especially from portfolio-intensive companies.
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Cette analyse a été réalisée par l'équipe PatSnap IP Intelligence, composée d'analystes en brevets, de stratèges en propriété intellectuelle et de scientifiques des données qui travaillent quotidiennement avec la base de données mondiale de PatSnap, qui regroupe plus de 2 milliards de données structurées issues de brevets, de dossiers de litiges, de publications scientifiques et de documents réglementaires.
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Références
- United States District Court for the District of Delaware — Case 1:25-cv-00415 (via PACER)
- Office américain des brevets et des marques — Centre des brevets
- Localisateur d'affaires PACER
- Cornell Legal Information Institute
- PatSnap — Solutions de veille en matière de propriété intellectuelle pour les cabinets d'avocats
Cet article est publié à titre purement informatif et ne constitue en aucun cas un avis juridique. Toutes les informations relatives aux affaires sont tirées de dossiers judiciaires accessibles au public. Pour en savoir plus sur les fonctionnalités de la plateforme, rendez-vous sur PatSnap.
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