The compute-radiation paradox: why legacy processors cannot run deep learning

Radiation-hardened processors used in space-qualified platforms lag commercial processors by several technology generations because they are designed around fault tolerance and long qualification timelines, not peak floating-point performance. According to research from the University of Luxembourg’s Interdisciplinary Centre for Security Reliability and Trust (SnT, 2023), onboard processing for deep learning algorithms “requires an improvement of several magnitudes in computing power compared to what is available with legacy, radiation-tolerant, space-grade processors in space vehicles today.” The same paper concludes that the next generation of AI processors for space will likely need to be heterogeneous systems combining diverse processing elements to overcome this gap.

This compute deficit carries direct operational consequences. Wuhan University’s 2022 paper on the Luojia3 intelligent remote sensing satellite highlights that high-resolution satellite sensors generate data at rates exceeding the processing capability of conventional onboard systems, creating a bottleneck between data acquisition and actionable information delivery. The paper describes how “the volume, weight, and computability of on-board systems are strictly limited by the harsh space environment,” making it extremely difficult to match compute capacity to the demands of diverse intelligent applications. To address this, the Luojia3 mission deployed a three-level edge computing architecture based on a System-on-Chip (SoC) optimised for low power consumption and expandable processing headroom.

The performance gap is further compounded for computationally intensive tasks like Synthetic Aperture Radar (SAR) processing, where real-time inference involves iterative signal processing algorithms operating on large data volumes. Research from the Beijing Institute of Technology (2017) showed that even the computationally dominant FFT operations in standard chirp scaling SAR algorithms must be reduced to fixed-point arithmetic to achieve feasible hardware cost — a compromise that must be carefully managed to prevent unacceptable accuracy loss in inference outputs. A companion study from the same group (2018) confirmed that a multi-node parallel acceleration approach with linearisation methods is needed even for floating-point implementations to satisfy real-time constraints, as documented in standards tracked by organisations such as IEEE.

How radiation corrupts AI inference — from sensor to output

Radiation in the space environment actively degrades electronic systems through two distinct mechanisms: cumulative damage from Total Ionizing Dose (TID) and transient bit-flipping Single Event Effects (SEE) caused by energetic particles including cosmic rays, trapped protons, and solar energetic particles. For AI inference pipelines specifically, where intermediate activations, weights, and control-flow states are processed in rapid succession across deep neural network layers, a single event upset can propagate silently through layers and produce incorrect outputs without triggering any visible fault flag — a failure mode with no equivalent in conventional deterministic flight software.

This radiation-hardware interaction pervades the entire signal chain — not just the processor. Research from Kyung Hee University (2019) on a radiation-hardened SAR ADC demonstrated that the flip-flop topology at the interface of analog and digital logic is particularly vulnerable to TID and SEE effects. The study proposed delay-based dual feedback flip-flop structures to restore radiation tolerance in successive-approximation-register ADCs used in space sensor readout systems. The implication for onboard AI is direct: sensor readout ASICs feeding data into neural network processors must themselves be radiation-hardened, meaning the radiation challenge extends from the sensor all the way to the inference output.

At the system level, Unibap AB’s 2020 paper directly confronts the trade-off between compute density and radiation tolerance. Commercial GPU architectures offer the compute throughput required for deep learning inference but are built on fine-geometry CMOS processes that are significantly more susceptible to SEE than older radiation-hardened devices. Unibap’s approach — building radiation-tolerant wrappers and mitigation techniques around heterogeneous GPU systems — accepts the underlying vulnerability of commercial silicon while adding system-level safeguards. A 2025 Toyota patent takes a complementary approach, computing the effect of radiation received by a processing device based on observed error information and implementing control to reduce the radiation impact — a feedback-based mitigation architecture applicable to mobile platforms in radiation environments.

The analog domain further illustrates the depth of the challenge. Space-grade ASICs built on 0.35 µm CMOS processes achieve noise floors of approximately 2099 electrons RMS, accepted as a deliberate trade-off for radiation survivability, as documented in a study from The Wakasa Wan Energy Research Center (2018) on a 32-channel ASIC for an X-ray APD detector aboard the International Space Station. Deploying AI accelerators — which rely on dense multiply-accumulate arrays in sub-10 nm processes — at equivalent radiation tolerance levels remains an unsolved manufacturing challenge, a gap also acknowledged in radiation standards maintained by ESA and NASA.

“A single event upset in an AI inference pipeline can propagate silently through deep neural network layers and produce incorrect outputs without triggering any visible fault flag.”

Power, mass, and thermal limits on onboard AI processing

Even if compute performance and radiation tolerance could be engineered independently, the satellite bus imposes hard physical constraints that commercial AI hardware cannot meet without significant adaptation. Small satellite and CubeSat platforms typically offer power budgets measured in single-digit to tens of watts, mechanical envelopes measured in litres, and thermal rejection paths limited by the vacuum environment and orbital eclipse cycles. Deep learning inference on commercial accelerators routinely demands tens of watts and significant board area, making direct transplant to space platforms infeasible.

ESA’s Φ-Sat-1 mission (2022) provides the most prominent in-orbit validation of these constraints. ESA selected the Intel Myriad 2 VPU for the Φ-Sat-1 CubeSat precisely because it offered an efficient ratio between computation and energy consumption for edge AI workloads. The mission demonstrated that only the most power-efficient AI accelerators — purpose-designed for edge inference with sub-watt to low-watt envelopes — are candidates for direct satellite integration, and even these required careful thermal and power management. This finding is consistent with broader edge computing standards tracked by IEEE and deployment guidance from ESA.

The FPGA-based alternative is examined in depth by the University of Pisa (2021), which benchmarked FPGA implementations of CNN inference against the Myriad 2 VPU for the CloudScout hyperspectral cloud detection task. While FPGAs offer flexibility and can be configured for radiation-tolerant operation — particularly with space-grade Xilinx or Microsemi devices — they consume more power per inference operation than purpose-built neural accelerators for equivalent throughput. The study confirmed that neither solution dominates across all metrics. The National Space Science Center of the Chinese Academy of Sciences (2022) proposed a parallel loop-unrolling strategy exploiting DSP arrays to maximise inference throughput on constrained on-orbit FPGAs, working within the fixed-resource ceiling of space-grade devices using architecture-level optimisations rather than process-level scaling.

The SAR use case illustrates the most extreme version of this constraint. The University of Naples Federico II (2020) projected execution times from commercial NVIDIA Kepler and Turing GPUs to avionic equivalents, confirming that GPU parallelism can satisfy real-time SAR focusing requirements — but only if an avionic-grade GPU platform becomes available. The authors acknowledged that “the unavailability of avionic platforms for this research” was a primary constraint, forcing them to scale commercial hardware benchmarks to estimate space-relevant performance. This projection-based approach signals how immature qualified GPU hardware remains for space AI applications, a gap also noted in procurement frameworks maintained by ESA.

Heterogeneous architectures, model compression, and task scheduling

Three broad architectural strategies have emerged as the engineering community’s response to the combined constraints of compute performance, radiation tolerance, and power limits. These strategies are not mutually exclusive — the most capable onboard AI systems combine all three.

Heterogeneous processing architectures

Heterogeneous SoC designs combine radiation-hardened host processors for housekeeping and fault management with higher-performance commercial or semi-commercial accelerators for AI inference workloads. The SnT reference architecture (2023) explicitly recommends heterogeneous systems as the standard model for next-generation onboard AI processors. Unibap AB’s radiation-tolerant GPU approach (2020) represents one commercial realisation of this concept. The Luojia3 three-level SoC architecture from Wuhan University (2022) similarly partitions workloads across processing tiers according to computation intensity and latency requirement. The National University of Defense Technology (2019) proposed transforming traditional satellites into space edge computing nodes capable of dynamically loading software in orbit and flexibly sharing onboard resources — a software-defined architecture that reduces reliance on mission-specific hardware qualification cycles measured in years.

Model compression and fixed-point quantisation

Model compression and fixed-point quantisation reduce the computational and memory demands of AI models to match available hardware. The SAR imaging work from Beijing Institute of Technology (2017) demonstrated partial fixed-point processing as an effective strategy for spaceborne DSP workloads. More directly relevant to neural network inference, the Shanghai Engineering Center for Microsatellites (2022) designed a lightweight deep learning detection algorithm specifically sized for on-orbit deployment, addressing the fundamental mismatch between standard deep network sizes and satellite compute budgets. For autonomous spacecraft control, Beihang University (2020) demonstrated that Radial Basis Function (RBF) neural networks can replace computationally intractable optimal control optimisations, generating real-time control policies via fast feedforward passes — showing that AI inference latency requirements can sometimes be relaxed by choosing architectures with favourable inference-time computational profiles.

Mission-oriented task scheduling

Mission-oriented task scheduling manages the allocation of constrained compute resources across competing inference tasks. Korea Aerospace Industries’ 2025 patent directly addresses this problem, proposing a method that distributes preprocessed image data to available hardware elements and executes AI models in parallel, explicitly designed for power-limited satellite environments. Airbus Defence and Space’s 2025 patent takes a complementary approach: using AI-based cloud detection to filter which imagery is worth processing at all, reducing total inference load through intelligent data triage at the mission planning level. Together, these two recent patents from major aerospace primes signal that the field is moving from laboratory demonstrations toward productised onboard AI systems.

Key organisations driving space AI hardware innovation

The most active and technically specific contributors to the engineering challenge of onboard satellite AI span both national space agencies and commercial aerospace primes, with a clear pattern of escalating patent activity from industry in 2025 signalling commercialisation pressure.

• European Space Agency (ESA) — Through the Φ-Sat-1 mission paper (2022), ESA demonstrated the first orbital deep neural network inference, establishing the Intel Myriad 2 VPU as a reference platform and qualifying power-efficiency as the primary selection criterion for space AI hardware. The Φ-Sat-1 paper remains the most widely cited in-orbit validation in the field.
• Chinese Academy of Sciences / National Space Science Center — Active across FPGA acceleration (YOLOX-s on-orbit FPGA, 2022) and satellite IoT edge computing architecture, reflecting China’s systematic national investment in intelligent satellite processing.
• Beijing Institute of Technology — Two major publications on real-time SAR imaging systems (fixed-point 2017, float-point 2018) establishing FPGA-ASIC heterogeneous acceleration as a viable approach for constrained spaceborne DSP workloads.
• Unibap AB (Sweden) — Commercial pioneer in radiation-tolerant GPU-based onboard processing (2020), targeting small satellite constellation operators who need cloud-like computing capabilities in orbit.
• University of Luxembourg SnT — Providing the most comprehensive reference architecture analysis for onboard AI/ML processing, articulating the heterogeneous systems paradigm as the industry consensus path (2023).
• Airbus Defence and Space / Korea Aerospace Industries — Recent patent activity (2025) from established primes signals commercialisation pressure to move beyond demonstrations toward productised onboard AI systems.

The overarching trend across this dataset is a shift from single-processor, application-specific flight computers toward heterogeneous, software-defined onboard computing platforms — driven by both commercial small satellite economics and the competitive pressure to deliver autonomous on-orbit intelligence. Qualification timelines and radiation testing remain the key bottlenecks separating laboratory demonstrations from flight-ready products, a structural gap that organisations including ESA and standards bodies such as ISO are working to address through updated space hardware qualification frameworks. For a broader view of global patent activity in this domain, PatSnap’s innovation intelligence platform tracks filings across all major jurisdictions.