Precursor Transport and Step Coverage Degradation in High-Aspect-Ratio Word Line Features

The fundamental obstacle to wafer-scale ALD uniformity in 3D NAND word line fill is geometry: the word line cavities that must be filled with tungsten are lateral, slit-like features with openings of approximately 25–30 nm, extending horizontally from a vertical gate line slit after the sacrificial nitride layer has been selectively removed. At these dimensions, the mean free path of ALD precursor molecules is no longer sufficient to sustain saturation chemisorption at the innermost recesses of each cavity — a problem that grows worse with every additional word line layer added to the stack.

Lam Research’s 2020 patent on metal fill processes for three-dimensional vertical NAND word lines discloses the primary industry response to this transport limitation: a boron nucleation layer formed from a diborane/hydrogen gas mixture is deposited as a conformal reducing agent before tungsten nucleation. The hydrogen in the mixture stabilises the diborane concentration; any instability in precursor concentration translates directly into film thickness non-uniformity across the wafer radius. This chemistry is specifically engineered to extend conformal coverage deeper into the lateral cavities than tungsten precursors alone could achieve.

The scaling trajectory makes this problem structurally worse over time. As documented in YMTC’s 2019 patent on 3D NAND flash memory fabrication, increasing stack heights from 32 to 64, 96, and 128 layers introduces progressive step coverage degradation: the depth of each word line cavity relative to the gate line slit opening increases, while simultaneously the thinner word line gaps required to accommodate higher layer counts exacerbate precursor transport limitations and increase capacitive coupling between adjacent word lines — an electrical signature of non-uniform fill that is directly measurable at test. According to the Micron Memory Japan review published in 2021, density has exceeded 10 Gb/mm² at 176 layers, placing extreme demands on every deposition process that must scale with layer count.

An important and often overlooked dimension of this challenge is that ALD uniformity in 3D NAND is not simply about maximising film thickness uniformity across the wafer. It also requires reproducibly controlling the spatial profile of fill within individual high-aspect-ratio features — a profile that must itself be uniform across millions of channel holes on the same wafer. YMTC’s 2018 patent on 3D NAND flash channel hole fabrication details a two-pass ALD oxide fill process designed to produce a controlled middle void inside the contact hole, enabling a flat-bottomed polysilicon deposition trench. The intentional non-uniformity of the first ALD pass — generating a tapered, top-wide, bottom-narrow oxide profile — is exploited to control the void geometry. If this within-feature profile is not reproduced consistently across the wafer, the subsequent polysilicon plug morphology will vary, and with it the electrical characteristics of every channel in the array.

Research from Nagoya University (2018) on neutral transport in high-aspect-ratio features confirms the underlying physics: at the bottom of deep features, the angular distribution of reactive neutrals is geometrically shadowed, producing a lower effective flux and therefore a reduced deposition rate. This within-feature non-uniformity is amplified by wafer-level variation in gas flow and temperature, linking the nanoscale transport problem directly to the wafer-scale process control problem.

How ALD Non-Uniformity Propagates into Threshold Voltage Spread

ALD non-uniformity in 3D NAND word line fill does not remain a process-level abstraction — it propagates directly into the electrical performance of every memory cell in the stack. If tungsten fill thickness or surrounding ONO dielectric conformality varies between the top and bottom word lines of a stack exceeding 100 layers, each cell will have a different effective gate oxide thickness, gate-to-channel coupling ratio, and trap density, producing a layer-dependent threshold voltage (Vth) that cannot be corrected at the programming level.

Research from IIT Kanpur (2022) on analytical modelling of 3D NAND flash cells confirms that greater than 100 stacked word line layers produces channel tapering and Vth non-uniformity between layers. The study proposes a non-uniform Gaussian vertical channel doping profile as a compensation strategy, but explicitly identifies the root cause as process-level non-uniformity in the word line stack — a compensation applied after the fact to a problem that originates in ALD and etch process variation.

“As cells are stacked up and scaled down simultaneously, the channel hole transitions from a macaroni to a nanowire cross-section — and the threshold voltage difference between the top and bottom cell depends primarily on XY scaling.”

Sungkyunkwan University’s 2022 TCAD simulation study on the impact of stacking and scaling on bit cell threshold voltages quantifies this geometric transformation: as the channel hole scales down while layer count increases, the cross-section transitions from a macaroni geometry to a nanowire geometry. This transition is driven by the taper introduced during deep plasma etching and the subsequent ALD fill of channel-hole sidewall ONO stacks. Critically, the threshold voltage difference (ΔVth) between the top and bottom cell is shown to depend primarily on XY scaling — meaning that radial variation in channel hole critical dimension (CD) across the wafer, arising from non-uniform etch rates and non-uniform ALD sidewall film thicknesses, translates into a wafer-level map of ΔVth variation.

The word line CD uniformity problem extends to the lithographic definition of word lines themselves. A 2025 patent from Jiangsu Yangheyang Microelectronics identifies that word lines proximal to select gates are defined at the edge of the lithographic exposure field, where pattern fidelity and CD uniformity are intrinsically worse than in the array interior. The patent proposes using sacrificial word line layers covered by select gate edges to transfer the non-uniformity to interior dummy word lines, improving the uniformity of functional word lines. This is explicitly a design-level workaround for a process-level ALD and etch CD uniformity limitation at the approximately 10 nm level.

Wafer Bow, Stress, and Edge Exclusion as ALD Uniformity Multipliers

Wafer-scale mechanical distortion is the second major axis of ALD uniformity failure in 3D NAND. The cumulative intrinsic stress of hundreds of alternating oxide and nitride layers produces wafer bow that is typically greater than 100 µm — far exceeding the tolerance of bonding tools and lithography scanners. For ALD specifically, a bowed wafer experiences non-uniform gas flow and non-uniform thermal contact with the susceptor across its surface, both of which translate into radial non-uniformity in film thickness and composition that is superimposed on the within-feature transport limitations described above.

YMTC’s 2018 patent on wafer stress compensation in the 3D NAND hybrid bonding process discloses the primary mitigation strategy: a tensile film deposited on the back side of the 3D NAND wafer before bonding reduces the bow differential between the 3D NAND wafer and the CMOS wafer to within ±30 µm, enabling contact misalignment to be controlled within 150 nm. Wuhan University’s 2024 patent takes a simulation-driven approach, constructing a finite element equivalent model of the 3D NAND wafer to map the thermal and mechanical stress distribution, then designing targeted back-side patterned etch processes on the common source line region to compensate local bow.

The wafer edge region presents a specific and persistent uniformity challenge. YMTC’s 2018 manufacturing method patent identifies that at the wafer extreme edge, the stacked layer topology is complex and contains recessed regions that create conditions for electrical arcing and film delamination during subsequent process steps. The disclosed solution uses a negative photoresist wafer edge exposure process to preserve edge photoresist, followed by selective etch of fill layers with a silicon nitride barrier layer — deposited by PECVD — acting as both etch stop and CMP stop. The same architecture reappears in YMTC’s 2020 update to this patent, confirming that edge non-uniformity remains an active engineering challenge rather than a solved problem.

According to standards bodies including SEMI, wafer flatness specifications for 300 mm substrates used in advanced logic are typically sub-10 µm across the full wafer; the greater than 100 µm bow observed in 3D NAND stacks represents an order-of-magnitude exceedance of these norms, requiring entirely new process integration strategies rather than incremental adjustments to existing ALD recipes.

CMP and Alternative Fill Processes as Uniformity-Recovery Mechanisms

Because ALD alone cannot guarantee wafer-scale planar uniformity across the topographically complex 3D NAND surface, chemical mechanical planarization (CMP) functions as the primary uniformity-recovery step after each major fill cycle. The interaction between ALD non-uniformity and CMP is bidirectional: ALD thickness variation creates a non-uniform starting surface for CMP, while CMP selectivity limitations can expose and damage adjacent layers if the ALD fill thickness is insufficient to provide an adequate polishing margin.

YMTC’s 2018 patent on 3D NAND channel hole planarization discloses that conventional multi-step CMP processes for polysilicon plug height uniformity suffer from over-etch damage to the ONO channel sidewall stack when the hard silicon nitride layer at the top of the O/N stack is removed by wet etching. The solution is a high-selectivity slurry that removes different materials at clearly differentiated rates, allowing CMP to stop precisely at the desired layer without a separate silicon nitride etch step. YMTC’s 2020 update to this patent reiterates that polysilicon plug height and morphology uniformity can be effectively improved through this selective CMP approach, directly improving product electrical performance.

Void and seam formation in narrow gap ALD oxide fill is a separate and well-documented failure mode. Sungkyunkwan University’s 2009 patent on neutral beam-assisted atomic layer chemical vapour deposition addresses exactly this problem: when ALD or ALD-like CVD processes fill trenches narrower than 65 nm, voids and seams form in the deposited oxide due to premature pinch-off of the feature opening. Neutral beams generated from ion beams are proposed to densify and heal the oxide layer after deposition, increasing film density and eliminating void-related uniformity failures. Though originally targeted at shallow trench isolation, the same physics governs oxide gap-fill in 3D NAND word line interlayer dielectrics.

The choice of fill process also determines the resistance of deposited films to downstream chemical attack. YMTC’s 2018 patent on top select gate cut line oxide fill discloses that conventional low-temperature oxide fill in the TSG slit is susceptible to etching by fluorine-containing gases used in subsequent tungsten gate formation processes. The solution is high-density plasma CVD (HDP-CVD) fill, which produces a denser oxide film resistant to fluorine attack. A non-uniform TSG slit fill will result in tungsten residues appearing with a spatial pattern correlated to the fill thickness non-uniformity map — making fill process selection a direct determinant of downstream yield. Semiconductor process standards from NIST and industry groups reinforce that film density and stoichiometry uniformity are as critical as thickness uniformity for downstream process compatibility.

YMTC’s 2018 patent on the gap layer between the common source tungsten wall and tungsten gates further demonstrates this principle: using an ONO sandwich structure (oxide-nitride-oxide) rather than a single low-temperature oxide as the gap layer substantially improves film quality, density, and breakdown voltage — all of which are functions of deposition uniformity within the high-aspect-ratio gate line slit. The IEEE Electron Devices Society has documented similar findings in planar device contexts, where ONO stack uniformity directly determines charge retention and endurance in charge-trap memory cells.

Closing the Control Loop: Metrology at the Limits of Optical Physics

A fundamental obstacle to achieving wafer-scale ALD uniformity is the inability to directly measure film thickness in buried layers of the multi-hundred-layer stack using conventional non-destructive techniques. Without a closed metrology loop, ALD process control cannot respond to run-to-run drift, and uniformity will degrade over time regardless of how well the deposition chemistry is engineered.

YMTC’s 2018 patent on 3D NAND storage device stack layer measurement states directly that optical ellipsometry cannot resolve individual layer thicknesses in a multi-hundred-layer stack because high optical correlation between layers at different depths prevents deconvolution. The proposed solution is a novel measurement coupon architecture: a groove is etched into a dielectric layer on the wafer, the full oxide-nitride stack is deposited into the groove so that cross-sectional layer edges are exposed on the groove sidewall, and SEM imaging of the alternating light-dark fringe pattern yields individual layer thicknesses. The companion patent from the same year extends this to a full wafer-scale thin film layer thickness measurement scheme, forming both a horizontal stack (the actual device stack) and a vertical stack (a perpendicular measurement structure) simultaneously on the same wafer, ensuring that the measurement structure reflects the exact deposition conditions of the device.

YMTC’s 2019 paper on metrology challenges in 3D NAND flash development situates these in-house metrology developments within the broader industry context. Unlike planar NAND, where top-down imaging suffices, 3D NAND requires inner structural control of channel hole profiles, multi-layer film uniformity, and opaque metal film thicknesses. The paper identifies mass measurement and mid-IR spectroscopy as new metrology modalities being deployed to address gaps in X-ray and optical techniques — each targeting a specific layer or material in the word line fill process sequence. The paper also lists high wafer bow, stress-induced overlay, and opaque film measurement as the three dominant metrology challenges arising from the three-dimensional vertical structure, and notes that as 3D NAND suppliers move beyond 150 layers, existing metrology tools are pushed to their limits. Without closed-loop metrology capable of resolving individual layer thicknesses non-destructively, ALD run-to-run uniformity control is structurally impossible. This metrology gap is, in a fundamental sense, the binding constraint on the entire ALD uniformity challenge — a point also recognised by NIST‘s semiconductor metrology programme and reflected in roadmaps published by the SEMI standards organisation.