Precursor transport and step coverage degradation in high-aspect-ratio word line features

The word line fill process in 3D NAND requires depositing tungsten into lateral, slit-like features with openings of approximately 25–30 nm — a geometry that is fundamentally adversarial to uniform film deposition. These recessed horizontal cavities extend tens to hundreds of nanometers into the oxide-nitride stack after selective removal of the sacrificial nitride layer, and the mean free path of ALD precursor molecules is insufficient to sustain saturation chemisorption at the innermost recesses as layer counts grow.

Lam Research’s 2020 patent on metal fill for three-dimensional vertical NAND word lines discloses that a boron layer formed from a diborane/hydrogen gas mixture is used as a conformal reducing agent, enabling nucleation of tungsten from a tungsten-containing precursor inside the horizontal word line cavities. The hydrogen serves to stabilize the diborane in the gas mixture — any instability in precursor concentration translates directly into film thickness non-uniformity across the wafer radius.

As documented by YMTC in its 2019 patent on 3D NAND Flash memory and fabrication, increasing stack heights from 32 to 64, 96, and 128 layers introduces progressive degradation in step coverage. The depth of each word line cavity relative to the gate line slit opening increases, and thinner sacrificial and interlayer dielectric layers required to accommodate more layers simultaneously exacerbate precursor transport limitations and increase capacitive coupling between adjacent word lines — an electrical signature of non-uniform fill.

An auxiliary fill challenge arises at the channel hole level, where ALD deposits oxide conformally into high-aspect-ratio contacts before polysilicon plug formation. A 2018 YMTC patent details a two-pass ALD oxide fill process designed to produce a controlled middle void inside the contact hole, enabling a flat-bottomed polysilicon deposition trench. The intentional non-uniformity of the first ALD pass — generating a tapered, top-wide/bottom-narrow oxide profile — is exploited to control void geometry. This illustrates a broader principle: in 3D NAND, ALD uniformity is not simply about maximising film thickness uniformity across the wafer, but also about reproducibly controlling the spatial profile of fill within individual high-aspect-ratio features, which must itself be uniform across millions of channel holes on the same wafer.

Research from Nagoya University (2018) on neutral transport in high-aspect-ratio features confirms that at the bottom of deep features, the angular distribution of reactive neutrals is geometrically shadowed, producing a lower effective flux and therefore a reduced deposition rate — a direct cause of within-feature non-uniformity that is amplified by wafer-level variation in gas flow and temperature.

Threshold voltage non-uniformity: the electrical signature of ALD variation

ALD non-uniformity in 3D NAND word line fill manifests electrically as a spread in threshold voltage (Vth) distributions across word line layers in the same string. When tungsten fill thickness or surrounding ONO/high-k dielectric conformality varies between the top and bottom word lines of a stack exceeding 100 layers, each cell experiences a different effective gate oxide thickness, gate-to-channel coupling ratio, and trap density — producing a layer-dependent Vth that cannot be corrected at the programming level alone.

Analysis from IIT Kanpur (2022) confirms that conventional 3D NAND Flash with greater than 100 stacked word line layers suffers from channel tapering and threshold voltage non-uniformity between cells in different word line layers. The study proposes a non-uniform Gaussian vertical channel doping profile as a compensation strategy, but identifies process-level non-uniformity in the word line stack as the root trigger.

“As cells are stacked up and scaled down simultaneously, the channel hole transitions from a macaroni to a nanowire cross-section — and the threshold voltage difference between top and bottom cells depends primarily on XY scaling.”

A TCAD simulation study from Sungkyunkwan University (2022) demonstrates that as cells are stacked up and scaled down simultaneously, the channel hole transitions from a macaroni to a nanowire cross-section. This geometric transformation — driven by taper introduced during deep plasma etching and subsequent ALD fill of channel-hole sidewall ONO stacks — causes the threshold voltage difference (ΔVth) between the top and bottom cell to depend primarily on XY scaling. Radial variation in channel hole critical dimension (CD) across the wafer, arising from non-uniform etch rates and non-uniform ALD sidewall film thicknesses, translates into a wafer-level map of ΔVth variation.

The word line uniformity problem extends to the geometrical definition of word lines themselves. A 2025 patent from Jiangsu Yangheyang Microelectronics identifies that word lines proximal to select gates are defined at the edge of the lithographic exposure field, where pattern fidelity and CD uniformity are intrinsically worse than in the array interior. The patent proposes using sacrificial word line layers covered by select gate edges to transfer non-uniformity to interior dummy word lines, thereby improving the uniformity of functional word lines. This is a design-level workaround for a process-level ALD and etch CD uniformity limitation at the approximately 10 nm level.

Wafer bow, stress, and edge exclusion as ALD uniformity constraints

3D NAND ALD uniformity is fundamentally constrained by wafer-level mechanical distortions arising from the cumulative intrinsic stress of hundreds of alternating oxide and nitride layers. This stress-induced bow is not merely a handling problem — it directly degrades the thermal and gas-flow uniformity that ALD depends on for conformal deposition across a 300 mm substrate.

A 2018 YMTC patent on wafer stress compensation in the 3D NAND hybrid bonding process states that 3D NAND wafer bow is typically greater than 100 µm — far exceeding the tolerance of bonding tools and lithography scanners. The patent discloses that a tensile film deposited on the back side of the 3D NAND wafer before bonding can reduce the bow differential between the 3D NAND wafer and the CMOS wafer to within ±30 µm, enabling contact misalignment to be controlled within 150 nm. For ALD specifically, a bowed wafer experiences non-uniform gas flow and non-uniform thermal contact with the susceptor across its surface, both of which translate into radial non-uniformity in film thickness and composition.

A 2024 patent from Wuhan University takes a simulation-driven approach to the same problem, constructing a finite element equivalent model of the 3D NAND wafer to map thermal and mechanical stress distribution, then designing targeted back-side patterned etch processes on the common source line region to compensate local bow. This approach, alongside YMTC’s metrology paper from 2019 — which identifies high wafer bow, stress-induced overlay, and opaque film measurement as the three dominant metrology challenges arising from the three-dimensional vertical structure — confirms that wafer bow is a systemic manufacturing constraint, not an edge case.

The wafer edge region presents a specific uniformity challenge confirmed across two YMTC manufacturing method patents (2018 and 2020). The persistent appearance of this edge non-uniformity problem across multiple patent generations underscores that the wafer periphery remains an unresolved locus of ALD process variation, even as array-interior uniformity improves. According to SEMI standards for wafer flatness, the edge exclusion zone for 300 mm wafers is typically defined at 2–3 mm — but in 3D NAND, the complex stack topology extends the effective non-uniformity zone significantly further inward.

CMP and dielectric fill: recovering uniformity after ALD

Because ALD alone cannot guarantee wafer-scale planar uniformity across the topographically complex 3D NAND surface, chemical mechanical planarization (CMP) functions as the uniformity-recovery step after each major fill cycle. The interaction between ALD non-uniformity and CMP is bidirectional: ALD film thickness variation creates local topography that CMP must remove, while CMP selectivity and endpoint control determine whether the ALD-deposited storage layer beneath is damaged.

A 2018 YMTC patent on channel hole planarization discloses that conventional multi-step CMP processes for polysilicon plug height uniformity suffer from over-etch damage to the ONO channel sidewall stack when the hard silicon nitride layer at the top of the O/N stack is removed by wet etching. The solution is a high-selectivity slurry that removes different materials at clearly differentiated rates, allowing CMP to stop precisely at the desired layer without a separate silicon nitride etch step and without entering the adjacent ONO storage layer. The 2020 update to this patent reiterates that polysilicon plug height and morphology uniformity can be effectively improved through this selective CMP approach, directly improving product electrical performance.

Void and seam formation in narrow gap ALD oxide fill is a distinct failure mode. Research from Sungkyunkwan University (2009) on neutral beam-assisted ALD apparatus addresses exactly this problem: when ALD or ALD-like CVD processes fill trenches narrower than 65 nm, voids and seams form in the deposited oxide due to premature pinch-off of the feature opening. Neutral beams generated from ion beams are proposed to densify and heal the oxide layer after deposition, increasing film density and eliminating void-related uniformity failures. The same physics governs oxide gap-fill in 3D NAND word line interlayer dielectrics, as confirmed by IEEE-published literature on high-aspect-ratio dielectric deposition.

For the top select gate (TSG) cut oxide fill, a 2018 YMTC patent discloses that conventional low-temperature oxide (LTO) fill in the TSG slit is susceptible to etching by fluorine-containing gases used in subsequent tungsten gate formation processes. The solution is to use high-density plasma CVD (HDP-CVD) fill, which produces a denser oxide film resistant to fluorine attack — demonstrating that the choice of fill process (ALD vs. HDP-CVD vs. PECVD) directly determines the uniformity of downstream process steps. A non-uniform TSG slit fill will result in tungsten residues appearing with a spatial pattern correlated to the fill thickness non-uniformity map.

A further YMTC patent from 2018 shows that using an ONO sandwich structure (oxide-nitride-oxide) as the gap layer between the common source tungsten wall and word line tungsten gates, rather than a single low-temperature oxide, substantially improves film quality, density, and breakdown voltage — all of which are functions of deposition uniformity within the high-aspect-ratio gate line slit. According to NIST materials science standards, film density and dielectric breakdown voltage are direct proxies for deposition uniformity and the absence of void or seam defects in deposited oxide layers.

Stack thickness metrology: closing the ALD process control loop

A fundamental obstacle to achieving wafer-scale ALD uniformity in 3D NAND is the inability to directly measure film thickness in buried layers of the multi-hundred-layer stack using conventional non-destructive techniques. Without closed-loop metrology, ALD run-to-run uniformity control is impossible — process drift is only detectable after post-process electrical testing, which is too late for yield-effective intervention.

A 2018 YMTC patent states directly that optical ellipsometry cannot resolve individual layer thicknesses in a stack because the high optical correlation between layers at different depths prevents deconvolution. The same patent proposes a novel measurement coupon architecture: a groove is etched into a dielectric layer on the wafer, the full oxide-nitride stack is deposited into the groove so that cross-sectional layer edges are exposed on the groove sidewall, and SEM imaging of the alternating light-dark fringe pattern yields individual layer thicknesses. This non-destructive (or minimally destructive) technique enables process control feedback for the ALD deposition steps.

A companion 2018 YMTC patent extends this to a full wafer-scale thin film layer thickness measurement scheme, forming both a horizontal stack (the actual device stack) and a vertical stack (a perpendicular measurement structure) simultaneously on the same wafer, ensuring that the thickness measurement structure reflects the exact deposition conditions of the device. This dual-structure approach is a direct acknowledgement that ALD uniformity verification cannot rely on off-wafer or surrogate measurements.

YMTC’s 2019 metrology challenges paper situates these in-house developments within the broader industry context: unlike planar NAND, where top-down imaging suffices, 3D NAND requires inner structural control of channel hole profiles, multi-layer film uniformity, and opaque metal film thicknesses. The paper identifies mass measurement and mid-IR spectroscopy as new metrology modalities being deployed to address gaps in X-ray and optical techniques — each targeting a specific layer or material in the word line fill process sequence. As 3D NAND suppliers move beyond 150 layers, existing metrology tools are pushed to their limits. This is consistent with the trajectory documented by WIPO in its annual Global Innovation Index, which identifies semiconductor process control as one of the most patent-dense technology areas globally, reflecting the intensity of unresolved engineering challenges at the frontier of scaling.

The metrology gap is not merely an academic concern: if the film stack thickness cannot be accurately measured non-destructively, ALD process control loops cannot be closed, and run-to-run uniformity will degrade. The entire 3D NAND metrology ecosystem is under strain at greater than 150 layers, with X-ray, mass measurement, and mid-IR spectroscopy emerging as necessary complements to optical tools. This represents a second-order constraint on ALD uniformity — the process may be capable of better uniformity than current metrology can verify or control.