ASML EUV and High-NA lithography technology roadmap

ASML’s Lithography Patent Portfolio: Scale, Status, and Filing Trends

ASML holds 4,995 lithography-related patents as of 2026, distributed across 2,020 active patents, 1,367 inactive patents, and 866 pending applications — a portfolio that averages 113 forward citations per patent, signalling exceptional technical influence across the semiconductor supply chain. Geographic concentration sits in US, EP, and CN jurisdictions, reflecting the company’s strategy of protecting core innovations in every major chip-manufacturing region.

Peak filing activity in 2019–2023 — averaging more than 400 patents per year — aligns precisely with EUV’s commercial ramp at leading foundries. This is not coincidental: as the NXE:3400 and NXE:3600 series entered high-volume manufacturing, ASML’s engineers were simultaneously solving the engineering challenges of the next platform, generating a sustained wave of IP. According to WIPO, semiconductor lithography consistently ranks among the highest-citation technology fields in global patent databases, and ASML’s 113-citation average reflects that standing.

Three Strategic Phases: DUV Maturation to High-NA EUV Deployment

ASML’s technology roadmap from 2010 to 2026 divides cleanly into three strategic phases, each defined by a distinct resolution regime, manufacturing node target, and IP investment profile. Understanding these phases is essential for R&D strategists benchmarking their own semiconductor innovation timelines against the industry’s dominant equipment supplier.

Phase 1: DUV Maturation (2010–2016)

During this phase, ASML perfected ArF immersion lithography at 193nm wavelength. NXT:1980Di systems achieved NA 1.35 with water immersion, enabling 38nm half-pitch resolution, while multi-patterning techniques — including LELE and SAQP — extended DUV to 10nm-class nodes. Computational lithography advances in source-mask optimisation improved process windows by 15–20%. Simultaneously, EUV pre-production tools (NXE:3100, 10W source power) were deployed at customer sites, and collector mirror lifetime was extended from fewer than 1,000 hours to more than 10,000 hours through hydrogen radical cleaning — a critical enabler for eventual commercial viability.

Phase 2: EUV Commercialisation (2017–2023)

The NXE:3400 series entered high-volume manufacturing with 0.33 NA, 125 WPH throughput, and 125W source power, enabling 7nm logic metal layers and DRAM capacitor patterning with overlay performance below 2nm (3σ). By 2021–2023, the NXE:3600D and NXE:3800E pushed throughput to 160 WPH and 220 WPH respectively, with source power exceeding 250W. By 2023, leading foundries had deployed more than 150 EUV scanners for 7nm, 5nm, and 3nm production. EUV reduced multi-patterning steps by 30–50%, improving yield and cycle time — and ASML captured 100% market share in EUV lithography. Standards bodies including SEMI have documented how EUV adoption reshaped the entire mask and process infrastructure ecosystem during this period.

“By 2023, ASML had captured 100% market share in EUV lithography, with leading foundries deploying more than 150 EUV scanners for 7nm, 5nm, and 3nm production — and EUV reduced multi-patterning steps by 30–50%.”

Phase 3: High-NA EUV Deployment (2024–2026+)

The first EXE:5000 High-NA EUV systems shipped to Intel in 2024 for 1.8nm node development, with early high-volume manufacturing adoption by leading foundries projected for 2025–2026 for sub-2nm logic. ASML maintained >80% market share in high-end DUV steppers during the DUV maturation era, a dominance that has since translated entirely into EUV. The Semiconductor Industry Association has identified High-NA EUV adoption as a critical pathway for sustaining Moore’s Law scaling through the 2020s.

High-NA EUV Architecture: What Changes at 0.55 NA

High-NA EUV systems achieve 0.55 NA — a 67% increase over the 0.33 NA of standard EUV — through a fundamentally redesigned optical architecture that introduces anamorphic optics, an expanded mirror count, and a new reticle format. These changes collectively enable 8nm single-exposure resolution, eliminating the need for multi-patterning at the 1.8nm and 1.4nm logic nodes.

The EXE:5000/5200 systems use 8 mirrors in the projection optics module, compared to 6 in 0.33 NA systems. Each mirror must maintain less than 0.5nm RMS wavefront error across a 26mm × 33mm exposure field — a specification that required years of collaborative development between ASML and Zeiss SMT, which supplies the optical modules. Advanced pupil facet mirrors with selectively reflecting coatings ensure illumination uniformity across the anamorphic field. Metrology systems use light sources with the same polarisation state as the main beam for accurate target positioning, a patented innovation that directly enables the sub-8nm overlay control required at these nodes.

Five Core R&D Innovation Domains Driving the EUV Patent Strategy

ASML’s IP portfolio demonstrates deep vertical integration across five core innovation domains, each of which maps to a distinct engineering challenge in EUV and High-NA EUV systems. Patent analysis reveals that these domains are not siloed — innovations in one area (e.g., source power scaling) directly enable advances in another (e.g., throughput and metrology accuracy).

1. Laser-Produced Plasma EUV Light Sources

ASML’s EUV sources use high-power CO₂ lasers to vaporise tin droplets, generating 13.5nm wavelength plasma. Precision droplet generators produce 50μm tin droplets at 50 kHz frequency. A pre-pulse laser shapes each droplet into optimal geometry before the main pulse impact, while advanced metrology systems track droplet position with less than 1μm accuracy for a hit rate exceeding 99%. Source power scaled from 10W in pre-production NXE:3100 tools to more than 250W in the NXE:3800E, with targets exceeding 500W for High-NA HVM.

2. Advanced Projection Optics

Projection optics in High-NA EUV systems must achieve less than 0.5nm RMS wavefront error across a 26mm × 33mm exposure field. The transition from 6-mirror to 8-mirror systems for 0.55 NA required new manufacturing techniques for mirror polishing, multilayer coating deposition, and in-situ wavefront correction. Advanced pupil facet mirrors with selectively reflecting coatings provide the illumination uniformity that anamorphic fields demand.

3. Metrology Systems

Overlay performance below 2nm (3σ) in the NXE:3400 series required metrology innovations that have since been extended for sub-8nm overlay control in High-NA systems. Metrology light sources using the same polarisation state as the main beam enable accurate target positioning — a patented approach documented in ASML’s patent filings that directly addresses the challenge of measuring features that are smaller than the measurement wavelength.

4. Computational Lithography

Source-mask-lens optimisation (SMLO) algorithms maximise process windows for single-exposure patterning at aggressive pitches. Earlier source-mask optimisation (SMO) advances during the DUV era improved process windows by 15–20%, and these techniques have been substantially extended for EUV and High-NA EUV contexts. Computational lithography is now a core competitive differentiator, with ASML’s algorithms enabling single-exposure patterning at pitches that would otherwise require multi-patterning.

5. System-Level Integration

Pellicle technology matured for 5nm/3nm nodes during the NXE:3600/3800 era, protecting masks from contamination and enabling the yield levels required for high-volume manufacturing. System-level integration patents cover the co-optimisation of source, optics, stage, and metrology subsystems — the engineering challenge of making all five innovation domains work together within a single production tool. The IEEE has published extensively on how ASML’s systems integration approach represents a unique form of platform-level IP that is difficult to replicate through component-level innovation alone.

Beyond 2026: The Hyper-NA Roadmap and Sub-1nm Ambitions

ASML has announced plans for a 0.75 NA “Hyper-NA” EUV platform targeting sub-5nm single-exposure resolution for future 1nm-class nodes and beyond, though commercialisation is not expected before 2028. This roadmap extension follows the same pattern as previous platform transitions: ASML begins engineering the successor system while the current generation is still ramping in high-volume manufacturing.

The Hyper-NA roadmap raises fundamental physics and engineering challenges that go beyond incrementally scaling the High-NA approach. At 0.75 NA, the depth of focus narrows further, resist sensitivity and stochastic effects become dominant yield limiters, and the optical system complexity increases substantially. ASML’s 866 pending patent applications as of 2026 likely include significant activity in these areas, though the company has not publicly disclosed the specific technical directions being pursued.

For R&D leaders and IP strategists, the Hyper-NA announcement is a signal to begin landscape analysis now. Historical precedent from the DUV-to-EUV transition shows that the IP window for foundational innovations in a new platform closes early: ASML’s filing surge in 2019–2023 was the EUV commercialisation wave, not the EUV invention wave. The invention wave for Hyper-NA is likely already underway, as evidenced by the 866 pending applications in the current portfolio. Tracking these filings — and the corresponding activity from optical component suppliers, resist manufacturers, and metrology vendors — is essential for any organisation with a stake in sub-2nm semiconductor manufacturing. Data from EPO patent analytics confirms that lithography-adjacent technology domains including EUV resists, mask blanks, and actinic inspection are all showing accelerating filing rates consistent with a platform transition cycle.