What Back-Side Power Delivery Is and Why It Matters at Sub-5nm

Back-side power delivery is an interconnect architecture in which power and ground rails are routed through the wafer’s back side — beneath the transistor layer — rather than through the same front-side metal stack that carries signal interconnects. In a conventional integrated circuit, both VDD and VSS rails coexist with dense signal wiring in the front-side metal layers (FEOL and BEOL), creating a structural competition for routing resources that imposes a ceiling on standard cell scaling. As documented in patent filings from IBM, back-side power rails formed beneath the transistor fins have been proposed specifically to relieve this constraint and enable technology scaling beyond the 5nm node.

The core problem that BSPDN addresses is IR drop. At advanced nodes with approximately 10–20 or more metal layers, front-side power delivery through thin copper lines suffers from high resistivity. According to patent documentation from Adeia Semiconductor Bond Technologies, a typical device must be designed to tolerate approximately 10% power delivery loss — a voltage drop — through the metal stack. As transistor density increases with each successive process node, the number of metal layers grows, effectively lengthening the path of power-carrying conductors to active devices. Reduced via cross-sections and increased line lengths compound the impedance problem, making front-side power delivery increasingly costly in terms of both energy and area.

BSPDN resolves this by enabling shorter, wider, and thicker conductors routed on the back side. Back-side wires have substantially lower resistance than the narrow front-side wires constrained by signal-routing pitch requirements. This directly reduces power delivery losses and on-chip IR drop. As Adeia’s interposer patent explains, removing power from the front-side stack also preserves those metal layers exclusively for signal routing and reduces BEOL complexity — a compound benefit that accelerates scaling.

Buried Power Rails, Back-Side Contacts, and Transition Vias

The practical realization of BSPDN requires three interconnected structural elements working in concert: buried power rails (BPRs) situated beneath the transistor layer, back-side contacts linking transistor source/drain regions directly to those rails, and transition vias connecting the back-side network to front-side supply nodes where hybrid architectures are required. Each element addresses a distinct fabrication and electrical challenge.

Self-Aligned Back-Side Contacts

IBM’s 2024 patent on self-aligned back-side contact integration describes a semiconductor device in which at least one back-side power rail is formed beneath transistor source/drain epitaxial regions, separated by a back-side inter-layer dielectric. A first back-side contact directly connects a selected source/drain epitaxial region to the back-side power rail, while other epitaxial regions retain contact placeholders. The key advantage over alternative designs is the avoidance of middle-of-line (MOL) congestion and routing restrictions. Crucially, source/drain epitaxial regions in adjacent CMOS cells retain access to M1 signal lines on the front side — meaning BSPDN does not sacrifice signal routing flexibility in exchange for its power delivery benefits.

The contact geometry is deliberate: a two-level tapered profile, with a larger critical dimension at the top and smaller at the bottom, ensures robust electrical connection to both the epitaxial region and the rail within the tight dimensional constraints of sub-5nm fabrication. IBM’s 2025 follow-on patent extends this by introducing a differentiated taper geometry — the back-side metal contact features a first tapered profile, while the back-side power rail itself features a second, distinct tapered profile — aimed at optimizing contact resistance and via fill reliability.

Transition Vias and Multi-Domain Power Architectures

ARM’s 2022 patent on buried power rail structures for memory devices demonstrates that BSPDN need not operate in complete isolation from the front-side power network. The architecture features both a frontside power network and a backside power network coexisting, bridged by buried transition vias (BTVs). The backside power network delivers power to a bitcell array through these BTVs, which couple the BSPDN to the frontside supply. This multi-domain architecture is particularly relevant for memory subsystems where bitcell arrays require independent supply management from the surrounding logic fabric — a requirement common in SoC designs tracked across PatSnap’s global patent database.

“Buried supply rails can serve a dual purpose: in addition to power delivery, at least one buried supply rail can act as a backside signal path for providing critical signal nets to logic circuitry — multiplying the utility of the back-side metal layer.”

ARM’s companion patent on buried metal techniques for critical signal nets extends this dual-use concept explicitly: at least one buried supply rail can act as a backside signal path for critical signal nets to logic circuitry. This multiplies the area benefit of adding back-side metal infrastructure well beyond simple power routing, effectively creating a second signal routing domain beneath the transistor layer that does not consume any front-side metal layers.

Package-Level Interposers and Pitch Transformation

A recurring challenge in BSPDN deployment is the pitch mismatch between the fine-pitch contact requirements at the die’s back side and the coarser pitches practical at the package substrate level. Adeia Semiconductor Bond Technologies addresses this in two 2025 patents. The interposer patent describes a power redistribution element hybrid-bonded to the active die’s back side, with a first set of contact pads on its front face at fine pitch to match die via landing requirements, and a second set on its back face at coarser pitch for package-level connectivity. This pitch transformation enables easier and lower-cost BSPDN deployment in volume manufacturing.

Adeia’s second patent introduces a reconstituted element approach: the die is embedded in an insulating material alongside back-side delivery infrastructure, with embedded power rails extending from the front surface to the back surface and connected to circuit devices via through-vias from the die’s back side. This modular solution enables BSPDN without requiring full monolithic wafer-level processing, broadening the range of manufacturing contexts in which back-side power delivery can be deployed — a consideration relevant to standards bodies such as JEDEC as packaging integration standards evolve.

How BSPDN Directly Increases Transistor Density

BSPDN increases transistor density through a direct area-liberation mechanism: by removing power rails from the front-side metal stack, it frees those routing layers entirely for signal interconnects and permits standard cell height reduction. Smaller standard cells mean more transistors per unit die area — the foundational metric of process node advancement. IBM’s 2025 patent on improved contact structures for power transfer states this explicitly: BPR technology “releases resources for dense logic interconnects that limit modern processor performance, enabling further scaling of standard logic cells by removing the overhead area occupied by power rails, and allows implementation of thicker, lower-resistance power rails with reduced IR drop.”

The density benefit compounds through a secondary mechanism: signal integrity improvement. The physical separation of power delivery from signal transmission reduces the probability that power delivery noise couples into signal lines — a growing concern at high switching frequencies in dense logic blocks, as noted in Adeia’s 2025 BSPDN patent. Cleaner signal environments allow tighter design margins, further enabling cell compaction.

Power Gating Through Dummy Transistors

IBM’s 2025 patent on power-gate dummy transistors for BSPDN introduces an architectural refinement that converts area overhead into productive circuit space. In conventional BSPDN schemes, power is delivered from the back side through the BEOL unchecked regardless of circuit utilization. IBM’s device inserts a power-gate transistor in series between a dummy transistor (connected to the BSPDN) and the functional circuit, with the BEOL controlling the gate transistor’s on/off state. This allows the circuit to cut power to inactive functional blocks, reducing static power consumption. The architecture exploits back-side delivery to serve the dummy transistor regions — converting what would otherwise be overhead area into productive circuit space.

Key Patent Holders and the BSPDN Innovation Landscape

Three organizations dominate the BSPDN patent landscape based on the filings analyzed, each with a distinct technical focus that reflects their position in the semiconductor value chain. The majority of substantive BSPDN patents date from 2022 to 2025, indicating an active and rapidly evolving technology domain with broad industry consensus that BSPDN is essential for sub-5nm and sub-2nm process nodes — a direction aligned with roadmaps tracked by the Semiconductor Industry Association and standards bodies including IEEE.

International Business Machines Corporation (IBM)

IBM is the most prolific assignee in the analyzed data for structurally specific BSPDN patents. IBM’s filings span three distinct areas: self-aligned back-side contacts (2024), improved contact geometry for power transfer with differentiated taper profiles (2025), and power-gated BSPDN architectures using dummy transistors (2025). The breadth of IBM’s portfolio — from fabrication process innovation through cell-level integration to power management architecture — positions the company as the foundational technical contributor in the BSPDN space. IBM’s work on the patented contact taper geometry addresses the sub-5nm fabrication challenge of maintaining via fill reliability at shrinking critical dimensions.

Adeia Semiconductor Bond Technologies

Adeia focuses on packaging-level and hybrid-bonding-level enablement of BSPDN. Their two 2025 filings cover power redistribution interposers with pitch transformation and reconstituted element-based back-side power rails. Adeia’s approach emphasizes modular, lower-cost deployment pathways — particularly relevant to advanced packaging integration where direct fine-pitch back-side contacts to package substrates may be impractical in volume manufacturing. This positions Adeia’s intellectual property as enabling infrastructure for fabless and OSAT players seeking to deploy BSPDN without full monolithic wafer-level processing.

ARM Limited

ARM contributes system-level and memory-subsystem BSPDN implementations. ARM’s 2022 patents address multi-domain power supply for memory bitcell arrays (using BTVs to bridge front-side and back-side power networks) and dual-function buried metal layers for both power delivery and critical signal nets. ARM’s filings are notable for extending BSPDN benefits beyond simple power routing into signal routing optimization — a perspective that reflects ARM’s position as a processor IP licensor whose designs must be implementable across a wide range of process nodes and foundry partners.