Canon nanoimprint lithography roadmap 2015–2026

How J-FIL works and why Canon bet on nanoimprint lithography

Canon’s nanoimprint lithography technology, marketed as Jet and Flash Imprint Lithography (J-FIL), achieves sub-10nm features by eliminating the wavelength constraint that limits optical lithography entirely. Instead of projecting light through a lens, J-FIL deposits low-viscosity UV-curable resist field-by-field via inkjet, presses a patterned template into the resist, allows capillary action to fill the template’s relief features, then UV-crosslinks the pattern and separates the template — leaving a patterned resist on the substrate. Resolution depends on template quality, not wavelength, enabling sub-10nm features without optical proximity correction.

The strategic logic is straightforward: EUV systems from ASML cost approximately $150–200M per unit and require extensive optical proximity correction at every advanced node. Canon’s NIL approach, by contrast, performs 1:1 pattern transfer from template to substrate — no OPC, no plasma light source, no complex projection optics. For cost-sensitive applications where EUV’s resolution advantage is unnecessary, Canon projects a 50–70% cost-of-ownership reduction.

Canon’s early development centred on the FPA-1100NZ2 single-station pilot tool, which established baseline capabilities between 2015 and 2016: overlay accuracy of 5–7nm (3σ), throughput of 15 wafers per hour, defectivity around 1 defect/cm², and template life of fewer than 100 wafers. Each of these metrics needed substantial improvement before high-volume manufacturing (HVM) was viable — and the decade-long engineering campaign to close those gaps forms the core of Canon’s NIL story.

From 15 to 90 wafers per hour: the FPA-1200NZ2C cluster breakthrough

The FPA-1200NZ2C’s four-station cluster architecture was the single most important throughput innovation in Canon’s NIL program. By sharing common infrastructure across four independent imprint stations and introducing a multi-field dispense method for parallel resist dispensing, Canon multiplied single-station output into a cluster throughput that meets semiconductor industry HVM requirements.

The fill time bottleneck was the critical engineering challenge. In 2016, resist fill required 1.2–1.5 seconds per field, constraining single-station output to 15–17 wafers per hour. Canon’s optimised drop patterns and dispense algorithms reduced fill time to 1.1 seconds by 2018, enabling 22.5 wafers per hour per station and 90 wafers per hour across the cluster. Simultaneously, the FPA-1200NZ2C incorporated automated template loading and particle inspection, and an integrated metrology system for in-line overlay and defect monitoring.

Particle contamination presented an existential threat to the economics of contact-based patterning. Hard particles on the template or wafer surface create permanent template damage. Canon’s analysis showed that to meet a 1,000-wafer template life target, particle adders must be kept below 0.001 particles per wafer pass — an extremely stringent requirement that drove the system’s environmental control architecture. Canon demonstrated template life of 81 lots using a contact test mask, confirming that the 1,000-wafer threshold was achievable. Non-fill defectivity was reduced to below 1.0 defect/cm² for both full fields and edge fields.

Overlay accuracy: the decade-long precision chase from 7nm to 2.5nm

Overlay accuracy — the ability to align successive patterned layers to within a specified tolerance — is the most critical performance metric for any lithography system targeting advanced nodes. Canon’s NIL program reduced overlay error by more than half over four years, from 5–7nm (3σ) in 2017 to 2.5nm single-machine overlay across the wafer by 2018, with sub-3nm overlay achieved from 2020 onward.

Two innovations drove the overlay improvement. First, Canon’s Through-the-Mask (TTM) Moiré alignment system uses spatial phase interferometry to measure multiple alignment marks within each imprint field during the imprinting sequence itself. Dual dipole illumination reduced measurement noise, and wavelength optimisation improved robustness across topography variations — together delivering more than 40% reduction in alignment measurement error. Second, High-Order Distortion Correction (HODC) applied correction to distortion terms up to K30 (30th order) using the existing magnification actuator, addressing wafer-scale and field-scale non-linear distortions that conventional overlay correction cannot reach.

“Canon’s NIL achieved 2.5nm single-machine overlay across the wafer by 2018 — a milestone that, combined with 90 wafers per hour cluster throughput, established the FPA-1200NZ2C as a credible HVM candidate for advanced memory nodes.”

Canon also demonstrated hp14nm dense silicon line patterning with 50nm depth on 300mm wafers using templates fabricated via self-aligned double patterning (SADP). CD uniformity reached below 2nm (3σ) and line edge roughness below 2nm — metrics that rival optical lithography at comparable nodes. According to IEEE and SPIE conference publications, these results confirmed NIL’s capability to address advanced memory nodes equivalent to approximately the 5nm logic node.

Canon’s i-line stepper portfolio: mature nodes, power devices, and advanced packaging

While developing NIL for leading-edge nodes, Canon simultaneously expanded its i-line stepper portfolio to address segments where EUV and immersion ArF are economically unjustifiable. This dual-track strategy ensures profitability across market cycles and hedges against the risk of slower-than-expected NIL adoption.

Large-panel and advanced packaging

The FPA-8000iW, launched in 2020, was the first Canon system supporting 515mm × 510mm panel substrates, offering 1.0µm resolution with a 52mm × 68mm exposure field — the finest resolution among large-panel lithography systems at its introduction. It targets panel-level packaging (PLP), a cost-effective approach to advanced packaging that processes multiple chips on a large panel rather than individual wafers. In 2023, Canon launched the FPA-5520iV LF2 Option with 0.8µm resolution across an ultra-wide 100mm × 100mm exposure field, with distortion aberration reduced to one-quarter of its predecessor — enabling heterogeneous integration and warped reconstituted substrate handling for fan-out wafer-level packaging.

Compound semiconductors and power devices

The FPA-3030i5a, introduced in 2020 for 50–200mm diameter substrates, supports SiC and GaN compound semiconductors targeting power devices for automotive electrification and 5G RF front-end modules. In September 2024, Canon released the FPA-3030i6 with a newly developed high-transmittance projection lens that delivers a 50% reduction in lens aberration versus previous models, raises productivity to 130 wafers per hour for 200mm wafers (from 123 wph), and maintains transmittance over the system lifetime through enhanced durability. The growing demand for SiC and GaN in electric vehicles, tracked by bodies including IEA, makes this segment a significant long-term revenue contributor for Canon.

Canon’s i-line competitive position benefits from ASML’s strategic focus on leading-edge EUV and Nikon’s retreat from lithography, leaving Canon as the primary supplier for cost-sensitive applications. According to WIPO‘s semiconductor equipment patent data, Canon maintains an active filing programme across both NIL and conventional stepper technologies, reinforcing its dual-track IP position.

First commercial deployment: the FPA-1200NZ2C at TIE and its competitive significance

In October 2024, Canon delivered the FPA-1200NZ2C to the Texas Institute for Electronics (TIE), a semiconductor consortium supported by The University of Texas at Austin — the first commercial NIL tool placement outside Canon’s own facilities. The system’s capabilities at delivery included a minimum linewidth of 14nm (5nm node equivalent), a roadmap to 10nm minimum linewidth (2nm node equivalent) with advanced template technology, and suitability for R&D of advanced semiconductors and prototype production.

The template replication infrastructure is a critical enabler of Canon’s cost position. The FPA-1100NR2 mask replication tool uses UV-NIL-based template-to-template replication to maintain below 1nm image placement accuracy across replicas, enabling cost distribution across 10–20 replicas per master template. This contrasts with EUV’s pellicle-dependent, high-defect-specification photomask infrastructure, where a single EUV mask can cost upward of $500,000. The SEMI standards body has noted the nascent state of NIL template supply chains as a key adoption hurdle — one Canon is addressing through the FPA-1100NR2 ecosystem.

Technology outlook: the 10nm NIL target and what the 2nm node requires

Canon’s roadmap beyond the 2024 commercial shipment targets a 10nm minimum linewidth, equivalent to the 2nm logic node, using advanced template technology. Achieving this requires advances across three interdependent domains: template fabrication, overlay control, and defectivity management.

Template fabrication at sub-10nm

Master templates for sub-15nm features are fabricated using e-beam direct write combined with self-aligned double or quadruple patterning (SADP/SAQP), with atomic layer deposition (ALD) used for surface modification. The FPA-1100NR2 replication process maintains below 1nm image placement accuracy across replicas, enabling cost distribution across 10–20 replicas per master. Extending this to 10nm features will require continued advances in e-beam resolution and ALD process control, areas where Canon has active patent filings as documented in the PatSnap innovation intelligence platform.

NIL adoption scenarios to 2030

Canon’s NIL program faces three plausible trajectories. In the optimistic scenario (assigned 30% probability in Canon’s analysis), a major memory manufacturer adopts NIL for 3D NAND critical layers by 2026, a successful 10nm template demonstration enables 2nm logic node entry by 2028, and NIL captures 15–20% of the advanced node lithography equipment market by 2030. The base case (50% probability) sees NIL as a niche solution for cost-sensitive memory and specialty logic, capturing 5–10% of the advanced node market — primarily in China and emerging fabs where EUV export restrictions create demand for alternatives. The pessimistic scenario (20% probability) involves EUV cost-of-ownership improvements and High-NA EUV introduction rendering NIL non-competitive, with template durability or defectivity issues preventing HVM adoption.

The 2025–2027 period is decisive. Successful memory HVM adoption and a 10nm capability demonstration would position NIL as a legitimate EUV alternative. Failure to secure major customer commitments would relegate it to a niche role. Regardless of outcome, Canon’s NIL program has already demonstrated that viable alternatives to EUV exist — a fact that, according to industry observers tracked by Nature Electronics and semiconductor policy analysts, has moderated ASML’s pricing power and encouraged continued innovation in lithography approaches.