Why copper is hitting a hard physical wall in BEOL

Copper’s failure as a BEOL interconnect material at advanced nodes is no longer a future risk — it is a present, quantified reality. Research from Samsung Semiconductor (2016) used first-principles density functional theory calculations to show that even theoretically ideal monocrystalline copper nanowires already exceed ITRS resistance projections at future technology nodes, due to quantum confinement alone. This means copper cannot physically meet roadmap requirements even under idealized conditions, with no grain boundary scattering, no edge roughness, and no interface defects.

In practice, the degradation is compounded by several scattering mechanisms. Research from Beijing Information Science and Technology University (2022), using a Boltzmann-transport-equation-based Monte Carlo simulation validated against copper, ruthenium, cobalt, and tungsten, confirmed that grain boundary scattering plays the dominant role in nanoscale interconnects, followed by surface roughness scattering and electron-phonon interactions. These effects are especially acute in M0 and M1 layers — exactly the local wiring tiers where density and scaling pressure are greatest.

The Cu/Ta barrier interface itself is a significant resistance contributor. University of Washington researchers (2009) demonstrated via semiclassical modeling that the Cu/Ta barrier interface generates substantial electron scattering losses, and that barrier layer presence can significantly decrease overall conductivity — consistent with experimental measurements. This finding underscores that scaling copper does not simply shrink a fixed-resistivity conductor: it progressively increases effective resistivity through both quantum and interface effects. The combined result is a hard physical wall that provides the primary technical driver for CNT interconnect research.

CNT electrical transport: the physics behind post-copper performance

Carbon nanotubes achieve their interconnect advantage through ballistic or quasi-ballistic electron transport — a fundamentally different conduction physics from metals. At sufficient lengths, CNTs conduct via ballistic transport with mean free paths exceeding one micron, far beyond those achievable in copper at sub-20 nm widths. This property, reviewed by Shanghai University’s School of Microelectronics (2022), places CNTs in a different performance class from all conventional metallic interconnect candidates, including ruthenium, cobalt, and molybdenum.

The intrinsic quantum resistance of a single SWCNT is approximately 6.45 kΩ, as discussed by University of Tehran researchers (2010), which makes individual tube deployment impractical for low-resistance wiring. The solution adopted across most architectures is to deploy dense bundles of parallel SWCNTs or MWCNTs, which reduce aggregate resistance proportionally to the number of conducting channels. MWCNTs offer an additional advantage: each concentric shell contributes parallel conducting channels, significantly reducing delay times compared to single SWCNTs. This multi-shell conductance is central to why MWCNTs have become the focus of via interconnect demonstrations — their geometry naturally maps to cylindrical via structures.

“Mixed and optimised CNT bundles achieve approximately 1.98× better delay performance than copper at 1000 µm interconnect lengths at the 22 nm node — a direct consequence of longer mean free paths under ballistic transport.”

SWCNT bundles have been shown to outperform copper on key figures of merit at advanced nodes. Equivalent RLC circuit models at the 22 nm node from Lovely Professional University (2016) demonstrated that SWCNT bundles achieve lower resistance — attributable to longer mean free paths — and reduced propagation delay compared to copper. The advantage is most pronounced at global and semi-global wiring levels, where wire lengths enter the regime where copper’s scattering-dominated transport becomes severely penalised. HSPICE simulations at 22 nm from Aligarh Muslim University (2013) confirmed that mixed and optimised CNT bundles achieve approximately 1.98× better delay performance than copper at 1000 µm interconnect lengths. Ballistic transport was also confirmed theoretically by researchers in Riga (2011), who identified it as the key differentiator from conventional metallic interconnects, attributing the low-loss conduction mechanism to ballistic transport.

BEOL architectures: vias, lines, and composite structures

Several distinct CNT-based BEOL architectures have been proposed, patented, and experimentally demonstrated — ranging from pure MWCNT via fills to cross-linked CNT trench lines and Cu-CNT composite structures. The most experimentally mature approach applies MWCNTs to vertical via structures. Fujitsu Laboratories (2009) demonstrated a landmark result: MWCNTs grown by CVD at temperatures as low as 365°C using Co catalyst nanoparticles were successfully integrated into via holes as small as 40 nm in diameter. The resulting CNT vias sustained current densities of 5.0 × 10⁶ A/cm² at 105°C for 100 hours without degradation — a reliability performance that copper cannot match at equivalent dimensions due to electromigration.

At the horizontal wiring level, a US patent filed by NARWANKAR (2013) describes a complete BEOL stack in which cross-linked CNTs fill damascene trenches as interconnect lines, grown on catalyst particles at precursor partial pressures above the transition point that shifts growth from parallel to cross-linked mode. This cross-linked morphology provides mechanical stability and three-dimensional connectivity within the trench. A companion PCT filing by SUNDARRAJAN (2013) elaborates the same architecture and explicitly connects CNT-filled vias to CNT-filled trenches in a complete two-layer BEOL interconnect stack.

IBM patented composite via structures that embed CNTs within copper, representing a transitional architecture. Filed in Korean jurisdiction (2006), the patent describes growing substantially parallel CNTs on metal catalyst pads within dielectric cavities, then filling the remaining void with copper. This composite approach leverages CNTs for their high current-carrying capacity through the via length while using copper to fill interstitial spaces and reduce total resistance. The scientific basis for this strategy was confirmed by the Technology Research Association for Single Wall Carbon Nanotubes (TASC, 2013), which demonstrated that Cu-CNT composites achieve conductivity of 2.3–4.7 × 10⁵ S/cm — comparable to bulk copper at 5.8 × 10⁵ S/cm — while delivering ampacity 100 times greater than copper, reaching 6 × 10⁸ A/cm².

TSMC holds an active patent (DE, 2013) that explicitly addresses the contact resistance problem by inserting carbon interfacial layers between CNT interconnect structures and metal lines above and below — recognising that contact resistance is a primary yield and performance risk in CNT BEOL integration. CEA’s patent (ES, 2015) addressed the geometric problem of routing CNT bundles in multiple directions, redirecting bundle axes between first and second directions to enable full planar routing without sacrificing the bundle’s conductance. For local interconnects at the smallest geometry tier, a US patent by ZHAO (2016) applies CNTs to local via interconnects and graphene nanoribbons to metal lines, while retaining conventional copper BEOL at intermediate and global levels — a tiered strategy that targets CNT advantages precisely where copper scaling is most impaired.

Thermal performance, electromigration resilience, and reliability

CNT interconnects offer compelling reliability advantages that become increasingly relevant as power densities and current densities rise at advanced nodes. COMSOL Multiphysics finite element simulations from SRM Institute of Science and Technology (2021) demonstrated that CNT interconnects withstand 68.75 times more power than aluminium and 32.35 times more than copper before reaching critical temperatures. This power handling advantage directly translates to superior electromigration immunity, as thermal excitation is the primary driver of copper electromigration failure.

“CNT interconnects withstand 32.35 times more power than copper before reaching critical temperatures — a direct thermal mechanism for eliminating the electromigration failures that constrain copper reliability at high current densities.”

The Cu-CNT composite direction is specifically targeted at improving both thermal stability and ampacity. A comprehensive survey from AIST’s CNT-Application Research Center (2018) established that Cu/CNT composites rival copper in electrical conductivity while offering superior thermal performance and mechanical robustness — key attributes for interconnects in automotive, aerospace, and advanced semiconductor applications. The study identifies the two principal unsolved challenges: achieving bulk composite performance that systematically exceeds copper, and achieving cost-effective, scalable fabrication. Both challenges reflect the gap between laboratory demonstrations and manufacturing readiness, and both are the subject of active patent filings from IBM, TSMC, and AIST-affiliated institutions.

The sub-threshold application domain is also served by CNT interconnect advantages. Researchers at the National Institute of Technology, Hamirpur (2022) formulated analytical models for the frequency-dependent complex conductivity of Cu-CNT composites at sub-threshold operating conditions. Using an ABCD matrix approach, the study analysed crosstalk, transfer gain, and Nyquist stability — demonstrating that Cu-CNT composites maintain signal integrity advantages over pure copper even at the low frequencies characteristic of ultra-low-power sub-threshold circuits. This finding extends the relevance of CNT interconnects beyond high-performance logic into the IoT and wearable computing domains, where sub-threshold operation is standard.

The thermal conductivity advantage of CNTs also has implications for heat spreading in dense interconnect stacks. A review from ETC srl, Bologna (2013) — covering horizontal and vertical arrays of single-wall and multi-wall CNT variants — noted that both electrical and thermal properties can potentially fulfil interconnect application requirements that copper cannot sustain at nanoscale, as confirmed by standards bodies including IEEE in their roadmap assessments for post-copper interconnect materials.

CMOS process integration: CVD growth and transfer methods

Practical BEOL insertion of CNTs requires CMOS-compatible processing, and this remains the field’s most significant manufacturing challenge. Chemical vapour deposition (CVD) is the leading growth method for IC-compatible CNT synthesis due to its mild reaction conditions, low cost, and scalability, as reviewed by Shanghai University (2023). However, the high temperatures typically required for high-density, high-quality CNT growth are incompatible with back-end thermal budgets, which generally cap at 400–450°C for processes applied after transistor formation.

Low-temperature synthesis of vertically aligned CNTs is therefore a critical enabling capability. Researchers at The Hong Kong University of Science and Technology (2020) reviewed the state of low-temperature synthesis with CMOS-compatible catalysts, emphasising the role of multilayer catalyst film design in generating alloyed catalyst nanoparticles that enable lower growth temperatures and higher CNT density. The catalyst engineering approach — using multilayer stacks rather than single-material films — is identified as the most promising pathway to reconcile growth quality with thermal budget constraints, consistent with WIPO patent filings from multiple institutions targeting sub-400°C growth processes.

An alternative to in-situ growth is the transfer method. CNRS-NTU-THALES Research Alliances (2021) demonstrated a thermocompression-based transfer process that separates the CNT growth and preparation steps from the target substrate entirely. High-accuracy transfer of CNT arrays onto designated areas with desired patterns was achieved, eliminating the thermal budget conflict by performing growth on a separate donor substrate. This decoupling strategy is considered particularly valuable because it allows CNT quality to be optimised independently of BEOL thermal constraints, and it permits integration of pre-characterised CNT material — a significant yield advantage over in-situ growth where defect density cannot be assessed before integration.

The integration of CNTs with through-silicon vias (TSVs) for 3D ICs is another emerging application. Researchers at Hangzhou Dianzi University (2020) demonstrated that CNT TSVs offer large capacitance and low inductance, enabling significant suppression of power distribution network impedance in 3D IC stacks compared to conventional metallic TSVs. Circuit models were validated against full-wave HFSS simulations, establishing credibility for the proposed CNT TSV equivalent circuit model. This application is directly relevant to chiplet-based architectures that are becoming standard at leading foundries, as tracked by SIA in its annual state-of-the-industry reports.

Key players and the direction of CNT BEOL innovation

Analysis of the source corpus — spanning more than 50 patents and publications — reveals several distinct clusters of institutional activity shaping CNT BEOL interconnect development. The innovation trend is clearly toward hybrid and composite structures rather than pure CNT replacements, with increasing focus on process integration and contact resistance reduction, reflecting the maturation from concept validation toward manufacturable solutions.

Academic institutions

Shanghai University’s School of Microelectronics is the most prolific academic contributor in this dataset, with publications in 2022 and 2023 covering both the state-of-the-art review of CNT on-chip interconnects and the specific challenges of CVD-grown CNT direct application to IC interconnects. Their work integrates electrical, thermal, and process dimensions across the full BEOL stack. Georgia Tech Research Corporation and inventor NAEEMI, AZAD hold US patents on ultra-low power SWNT interconnects for sub-threshold circuits, targeting the specific operating regime of ultra-low-power logic where CNT advantages are most compelling.

Industry and foundry IP

IBM holds multiple patents on CNT-Cu composite via structures, with filings recorded in Chinese jurisdiction (2007, 2010) and Korean jurisdiction (2006), establishing early IP in the composite via architecture where CNTs are co-deposited with copper in via cavities. Taiwan Semiconductor Manufacturing Co. (TSMC) holds an active patent on low contact resistance CNT interconnect apparatus, reflecting active IP development at a leading-edge foundry. CEA (Commissariat à l’Énergie Atomique) patented multi-directional CNT bundle interconnect geometries enabling routed BEOL connectivity, addressing the practical integration challenge of directional bundle placement in real routing layers. AIST through the Technology Research Association for Single Wall Carbon Nanotubes (TASC) contributed the foundational 100× ampacity measurement of CNT-Cu composites that underpins composite interconnect engineering. Fujitsu Laboratories contributed the most significant experimental demonstration in the dataset — low-temperature MWCNT via fabrication and current density reliability testing at 5.0 × 10⁶ A/cm² for 100 hours — establishing a concrete process benchmark for CNT via interconnects. Researchers and organisations can track the full competitive patent landscape using PatSnap’s innovation intelligence platform, which covers 2B+ data points across 120+ countries.