Why copper hits a hard physical wall in BEOL

Copper cannot physically meet roadmap resistance requirements at future technology nodes—not even under idealized conditions. First-principles density functional theory calculations by Samsung Semiconductor (2016) established that the lower resistance limits for monocrystalline copper nanowires already exceed International Technology Roadmap for Semiconductors (ITRS) projections, meaning quantum confinement alone is sufficient to disqualify copper as a viable BEOL conductor at advanced nodes, before any practical scattering mechanism is considered.

In practice, the degradation is compounded by multiple scattering mechanisms. Research from Beijing Information Science and Technology University (2022) using a Boltzmann-transport-equation-based Monte Carlo simulation—validated against Cu, Ru, Co, and W metals—confirmed that grain boundary scattering plays the dominant role in nanoscale interconnects, followed by surface roughness scattering and electron-phonon interactions. These effects are most acute in M0 and M1 layers, precisely the local wiring tiers under greatest scaling pressure.

The copper/barrier interface compounds the problem further. Semiclassical modeling by the University of Washington (2009) demonstrated that the Cu/Ta barrier interface generates substantial electron scattering losses, and that barrier layer presence can significantly decrease overall conductivity—consistent with experimental measurements. Scaling copper does not simply shrink a fixed-resistivity conductor: it progressively increases effective resistivity through both quantum and interface effects simultaneously. According to ITRS, these combined effects now constitute the central roadblock to sub-10 nm BEOL wiring.

CNT electrical transport: the physics behind post-copper performance

Carbon nanotubes outperform copper at advanced nodes because they conduct via ballistic or quasi-ballistic electron transport, with mean free paths exceeding one micron—far beyond those achievable in copper at sub-20 nm widths. This fundamental distinction in conduction physics, reviewed by Shanghai University’s School of Microelectronics (2022), means that CNT resistance does not scale adversely with wire cross-section in the same catastrophic manner as copper.

The intrinsic quantum resistance of a single SWCNT is approximately 6.45 kΩ, making individual tube deployment impractical for low-resistance interconnects, as noted by the University of Tehran (2010). The solution is dense bundles of parallel SWCNTs or MWCNTs, which reduce aggregate resistance proportionally to the number of conducting channels. MWCNTs offer a particular advantage: each concentric shell contributes parallel conducting channels, significantly reducing delay times compared to single SWCNTs. This multi-shell conductance geometry maps naturally to cylindrical via structures, which is why MWCNTs have dominated via interconnect demonstrations.

“Mixed and optimised CNT bundles achieve approximately 1.98× better delay performance than copper at 1000 µm interconnect lengths at the 22 nm node.”

At the 22 nm node, SWCNT bundle RLC circuit simulations from Lovely Professional University (2016) demonstrated lower resistance and reduced propagation delay compared to copper, attributable to longer mean free paths. The performance advantage is most pronounced at global and semi-global wiring levels where wire lengths enter the regime where copper’s scattering-dominated transport is most severely penalized. HSPICE simulations from Aligarh Muslim University (2013) confirmed the 1.98× delay advantage at 1000 µm lengths. Theoretical work using an effective media approach (Information Systems Management University, Riga, 2011) identified ballistic transport as the key differentiator from conventional metallic interconnects, confirming the low-loss conduction mechanism from first principles. According to IEEE published research, these transport advantages become increasingly decisive as technology nodes advance below 10 nm.

BEOL architectures: vias, lines, and composite structures

The most experimentally mature CNT BEOL architecture applies MWCNTs to vertical via structures. Fujitsu Laboratories (2009) achieved a landmark result: MWCNTs grown by CVD at temperatures as low as 365°C using Co catalyst nanoparticles were integrated into via holes as small as 40 nm in diameter, sustaining current densities of 5.0 × 10⁶ A/cm² at 105°C for 100 hours without degradation—a reliability performance copper cannot match at equivalent dimensions due to electromigration.

At the horizontal wiring level, patents have addressed both via and trench fill. A 2013 US patent (NARWANKAR) describes a complete BEOL stack in which cross-linked CNTs fill damascene trenches as interconnect lines, grown on catalyst particles at precursor partial pressures above the transition point that shifts growth from parallel to cross-linked mode. This cross-linked morphology provides mechanical stability and three-dimensional connectivity within the trench. The companion PCT filing (SUNDARRAJAN, 2013) elaborates the same architecture and explicitly connects CNT-filled vias to CNT-filled trenches in a complete two-layer BEOL interconnect stack.

IBM patented composite via structures that embed CNTs within copper—a transitional architecture. A 2006 Korean filing by International Business Machines Corporation describes growing substantially parallel CNTs on metal catalyst pads within dielectric cavities, then filling the remaining void with copper. This composite approach leverages CNTs for their high current-carrying capacity through the via length while using copper to fill interstitial spaces and reduce total resistance. The scientific basis was confirmed by TASC (2013) with the 100× ampacity result noted above.

TSMC’s 2013 patent (DE jurisdiction) explicitly addresses the contact resistance problem by inserting carbon interfacial layers between CNT interconnect structures and metal lines above and below—recognizing that contact resistance is a primary yield and performance risk in CNT BEOL integration. CEA’s 2015 patent (ES jurisdiction) addressed the geometric challenge of routing CNT bundles in multiple directions, redirecting bundle axes to enable full planar routing without sacrificing bundle conductance. For local interconnects at the smallest geometry tier, a 2016 US patent (ZHAO) applies CNTs to local via interconnects and graphene nanoribbons to metal lines, while retaining conventional copper BEOL at intermediate and global levels—a tiered strategy targeting CNT advantages precisely where copper scaling is most impaired.

Thermal performance, electromigration resilience, and reliability

CNT interconnects withstand 32.35 times more power than copper before reaching critical temperatures, according to COMSOL Multiphysics finite element simulations from SRM Institute of Science and Technology (2021)—and 68.75 times more than aluminum. This power handling advantage directly translates to superior electromigration immunity, since thermal excitation is the primary driver of copper electromigration failure at high current densities.

The thermal conductivity advantage of CNTs extends to heat spreading in dense interconnect stacks. A 2013 review from ETC srl, Bologna, notes that both electrical and thermal properties of CNT architectures—including horizontal and vertical arrays of single-wall and multi-wall variants—can potentially fulfill interconnect application requirements that copper cannot sustain at nanoscale. This dual electrical-thermal advantage is particularly relevant as power densities continue to rise with device scaling, a concern tracked by bodies including OECD in its semiconductor supply chain analyses.

The Cu-CNT composite direction specifically targets thermal stability and ampacity improvement. AIST’s CNT-Application Research Center (2018) presented a comprehensive survey establishing that Cu/CNT composites rival copper in electrical conductivity while offering superior thermal performance and mechanical robustness—key attributes for interconnects in automotive, aerospace, and advanced semiconductor applications. The study identifies two principal unsolved challenges: achieving bulk composite performance that systematically exceeds copper, and achieving cost-effective, scalable fabrication.

At sub-threshold operating conditions, Cu-CNT composites also maintain signal integrity advantages. The National Institute of Technology, Hamirpur (2022) formulated analytical models for frequency-dependent complex conductivity of Cu-CNT composites using an ABCD matrix approach, analyzing crosstalk, transfer gain, and Nyquist stability—demonstrating that Cu-CNT composites maintain signal integrity advantages over pure copper even at the low frequencies characteristic of ultra-low-power sub-threshold circuits.

CMOS process integration: CVD growth and transfer methods

The leading process integration barrier for CNT BEOL interconnects is thermal budget compatibility: high-quality CNT growth typically requires temperatures that exceed the 400–450°C cap for back-end processes applied after transistor formation. Chemical vapor deposition (CVD) is the leading growth method for IC-compatible CNT synthesis due to its mild reaction conditions, low cost, and scalability, as reviewed by Shanghai University (2023), but reconciling growth quality with thermal budget constraints remains the field’s central manufacturing challenge.

Low-temperature synthesis of vertically aligned CNTs is a critical enabling capability. Research from The Hong Kong University of Science and Technology (2020) reviewed the state of low-temperature synthesis with CMOS-compatible catalysts, identifying multilayer catalyst film design—using multilayer stacks rather than single-material films—as the most promising pathway to generating alloyed catalyst nanoparticles that enable lower growth temperatures and higher CNT density. According to NIST nanofabrication guidance, catalyst engineering of this type is a recognized approach to reducing CVD process temperatures for carbon nanomaterial synthesis.

An alternative to in-situ growth is the transfer method. CNRS-NTU-THALES Research Alliances (2021) demonstrated a thermocompression-based transfer process that separates CNT growth and preparation from the target substrate entirely. High-accuracy transfer of CNT arrays onto designated areas with desired patterns was achieved, eliminating the thermal budget conflict by performing growth on a separate donor substrate. This decoupling strategy allows CNT quality to be optimized independently of BEOL thermal constraints and permits integration of pre-characterized CNT material.

CNT interconnects are also being evaluated for three-dimensional integration. Research from Hangzhou Dianzi University (2020) demonstrated that CNT through-silicon vias (TSVs) offer large capacitance and low inductance, enabling significant suppression of power distribution network impedance in 3D IC stacks compared to conventional metallic TSVs. Circuit models were validated against full-wave HFSS simulations, establishing credibility for the proposed CNT TSV equivalent circuit model. This application domain aligns with the broader push toward 3D integration documented by imec and other leading semiconductor research institutes.

Key players and innovation trends in CNT BEOL IP

The CNT BEOL interconnect IP landscape is dominated by a small cluster of institutions whose contributions span experimental demonstration, process patents, and composite material characterization. Analysis of over 50 sources reveals a clear shift from concept validation toward manufacturable hybrid solutions.

Academic and research institutions

Shanghai University’s School of Microelectronics is the most prolific academic contributor in this dataset, with publications in 2022 and 2023 covering both the state-of-the-art review of CNT on-chip interconnects and the specific challenges of CVD-grown CNT direct application to IC interconnects, integrating electrical, thermal, and process dimensions. Georgia Tech Research Corporation and inventor NAEEMI, AZAD hold US patents on ultra-low power SWNT interconnects for sub-threshold circuits, targeting the specific operating regime where CNT advantages are most compelling.

Industry and foundry IP

IBM holds multiple patents on CNT-Cu composite via structures, with filings in Chinese jurisdiction (2007, 2010) and Korean jurisdiction (2006), establishing early IP in the composite via architecture. Fujitsu Laboratories contributed the most significant experimental demonstration in the dataset—low-temperature MWCNT via fabrication and current density reliability testing at 5.0 × 10⁶ A/cm² for 100 hours—establishing a concrete process benchmark. Taiwan Semiconductor Manufacturing Co. (TSMC) holds an active patent on low contact resistance CNT interconnect apparatus, reflecting active IP development at a leading-edge foundry for BEOL CNT integration. CEA patented multi-directional CNT bundle interconnect geometries enabling routed BEOL connectivity. AIST through the Technology Research Association for Single Wall Carbon Nanotubes (TASC) contributed foundational ampacity measurements—the 100× ampacity result—that underpin composite interconnect engineering.

The overall innovation trend is clearly toward hybrid and composite structures rather than pure CNT replacements, with increasing focus on process integration (CVD at low temperature, transfer methods) and contact resistance reduction. This reflects the maturation of the field from concept validation toward manufacturable solutions deployable in production BEOL flows. PatSnap’s patent analytics platform tracks this IP evolution across all major jurisdictions in real time.

“The innovation trend is clearly toward hybrid and composite structures rather than pure CNT replacements, with increasing focus on process integration and contact resistance reduction—reflecting the maturation from concept validation toward manufacturable solutions.”