Why contact resistance defines nanosheet FET performance at sub-3 nm

Parasitic source/drain contact resistance is the primary performance-limiting factor in nanosheet field-effect transistors (FETs) as the industry scales beyond the 3 nm node. As gate lengths shrink and channel resistance falls, the fraction of total device resistance attributable to the metal-semiconductor junction at the source and drain grows disproportionately — making contact engineering the decisive variable for drive current, switching speed, and power efficiency.

The dataset underpinning this analysis spans approximately 60 patent filings and peer-reviewed literature entries from 2000 to 2024, covering contact resistance reduction across a broad range of FET architectures. The most directly relevant subset focuses on nanosheet FETs, metal-semiconductor interface physics, and low-work-function contact engineering. Four dominant technical approaches emerge from this body of work: selective silicidation combined with metal fill processes; low-work-function metal selection to minimise Schottky barrier height (SBH); insertion of ultra-thin interfacial layers to depin the Fermi level; and contact geometry engineering through trench filling and nanosheet stack coverage. These strategies are frequently combined in advanced process flows targeting beyond-3-nm nodes.

Understanding these mechanisms is not merely academic. According to research published by IEEE, contact resistance now accounts for a substantial share of total transistor resistance in advanced nodes, and the industry consensus — reflected in roadmap documents from SEMI — is that contact engineering must advance in lockstep with gate-stack scaling to sustain performance gains.

Silicidation and full-stack metal fill: the industrial standard for nanosheet contact engineering

Selective silicidation at nanosheet channel ends followed by a continuous metal fill spanning the full vertical extent of the nanosheet stack is the most extensively patented and industrially mature approach to reducing source/drain contact resistance in nanosheet FETs. The core problem it solves is straightforward: conventional contact metallisation in scaled nanosheet devices fails to uniformly contact all nanosheet layers in a stack, leaving higher-resistivity current paths through some channels.

Applied Materials, Inc. has established the most comprehensive IP position in this space, with a process disclosed in a 2022 US filing and counterparts filed across WO, KR, JP, CN, and TW jurisdictions. The process involves three steps: etching the nanosheet stack to form source/drain regions within alternating nanosheet channel and sacrificial layers; depositing a silicide layer selectively at the ends of the nanosheet channel via selective silicidation to control effective channel length; and performing a metal fill process extending from the lowermost to above the uppermost nanosheet channel layer. The Chinese counterpart elaborates a variant in which separate masked silicidation steps are performed sequentially for n-type and p-type source/drain regions, enabling independent optimisation of contact metals for CMOS integration.

“By ensuring the metal fill extends continuously from the lowest to the highest channel layer, the effective contact area is maximised for each nanosheet layer — directly reducing total source/drain contact resistance.”

The silicide layer serves a dual function: it lowers the metal-silicon interfacial barrier and precisely controls the channel length, which is critical at sub-5 nm nodes where even nanometre-scale variations in effective channel length materially affect device characteristics. IBM’s patents from 2020 and 2024 address a related but distinct problem — the detrimental effect of source/drain material overfill on contact resistance — by filling trenches formed in the source/drain regions with metal-based materials.

At the device level, the importance of silicide contact quality was demonstrated in poly-Si nanosheet devices by researchers at National United University, Taiwan in 2017. Two-step annealing with a Ti capping layer produced an ultra-thin, uniform nickel silicide (NiSi) film with low sheet resistance. The resulting junctionless nanosheet FET with NiSi contact achieved a high driving current exceeding 10⁷ A and a measurable improvement in parasitic resistance over devices lacking silicide contacts, establishing NiSi as a viable silicide contact material for nanosheet FET architectures.

Low-work-function metals and Schottky barrier minimisation for n-type contacts

For n-type semiconductor junctions, achieving low or negative electron Schottky barrier height requires metals whose work function is close to or below the electron affinity of the semiconductor. This fundamental relationship — well-established in the physics literature and codified in standards from NIST — underpins metal selection for n-type nanosheet FET contacts. The practical consequence is that the wrong metal choice, regardless of process quality, produces a rectifying rather than ohmic junction, sharply degrading drive current.

The most quantitatively compelling demonstration of this principle comes from a 2018 study by National Taiwan University, which showed that indium (In) forms a near-ohmic contact with InSe due to favourable band alignment at the In-InSe interface. The resulting barrier height of only 50 meV and on-current of 410 µA/µm represent a benchmark for what low-work-function metal selection can deliver when band alignment is favourable. The 1981 patent by Lin, Hung Chang established the foundational principle that metals with low work functions heated to different temperatures produce ohmic contacts to n-type semiconductor regions while maintaining rectifying behaviour for p-type regions — a selective metallisation concept still embedded in modern CMOS nanosheet FET process flows.

The leakage implications of low-work-function metal contacts were analysed in a 2021 study from Jamia Millia Islamia, which proposed a low-work-function metal drain with a negative electron SBH (≤0 eV) to suppress lateral band-to-band tunnelling (L-BTBT) in nanowire FETs. The analysis demonstrated that a metal drain with SBH ≤ 0 eV substantially minimises OFF-state leakage compared to both conventionally doped and junctionless nanowire FET counterparts — a finding directly relevant to nanosheet FETs, where the same physical trade-off between contact barrier height and leakage applies.

For aluminium on silicon, RWTH Aachen University demonstrated in 2021 that combining Al with a thin silicon nitride interfacial layer achieves a theoretical SBH of only 0.2 eV to the silicon conduction band after Fermi-level depinning — a result that illustrates the combined power of metal work function selection and interface engineering. The work also confirmed that without the interfacial layer, Fermi-level pinning would prevent Al’s low work function from translating into a reduced barrier.

Fermi-level depinning through interfacial layer engineering: overcoming the dominant obstacle

Fermi-level pinning (FLP) is the dominant obstacle to work-function-dependent Schottky barrier reduction in n-type nanosheet FET contacts. Interface states at the metal-semiconductor junction effectively fix the Fermi level independently of metal work function, negating the benefit of low-work-function metal selection entirely. Dedicated interfacial layer engineering is therefore not optional at advanced nodes — it is a prerequisite for realising the theoretical advantage of low-work-function metals.

Acorn Technologies, Inc. established the foundational IP framework for this approach in a 2005 US patent, disclosing an electrical device incorporating an interface layer between a metal and a Si-based semiconductor that is sufficiently thick to depin the semiconductor Fermi level while remaining thin enough to permit tunnelling current flow. The resulting specific contact resistance can be as low as 1 Ω-µm². Corresponding Taiwan patents from 2005 and 2010 detail that such interface layers may consist of nitrogen, oxygen, oxynitride, arsenic, hydrogen, and/or fluorine passivating materials as thin as a single monolayer, enabling contact resistivities below 10 Ω-µm². Acorn’s 2022 Taiwan patent extends this concept to group III/V atomic monolayer insertion at metal-group IV semiconductor interfaces, where ordered monolayers chemically bonded to the semiconductor surface provide both FLP mitigation and a direct low-barrier conduction path.

For 2D-material nanosheet channels, boron nitride (BN) monolayer insertion has emerged as the most theoretically and experimentally validated depinning strategy. A 2015 computational study from the University of Twente showed that inserting a BN monolayer between low-work-function metals — including cobalt (Co) and nickel (Ni) — and MoS₂ disrupts the metal-MoS₂ interaction responsible for Fermi-level pinning, restores the MoS₂ electronic structure, and decreases the effective metal work function by up to 2 eV, enabling alignment of the Fermi level with the MoS₂ conduction band. This is a striking result: a single atomic layer of BN effectively converts a pinned, high-barrier contact into a low-barrier ohmic contact.

Experimental confirmation came from the Institute of High Performance Computing, Singapore in 2014, where nickel-etched-graphene electrodes on MoS₂ achieved contact resistance as low as 200 Ω·µm. The authors attributed this to the much smaller effective work function of the nickel-graphene composite electrode and enhanced tunnelling at zigzag graphene edges. This result, reported in Nature-indexed journals, established graphene interlayers as a practical route to sub-200 Ω·µm contact resistance for 2D-material nanosheet channels.

Patent landscape and key innovation players: who owns the contact resistance IP

Applied Materials, Inc. is the dominant patent assignee in nanosheet FET contact resistance reduction, with filings across US, WO, KR, JP, CN, and TW jurisdictions between 2022 and 2024. Their process integration approach — selective silicidation followed by continuous metal fill across the full nanosheet stack — represents the most mature industrial pathway to sub-3-nm node contact engineering. The multi-jurisdictional filing strategy signals a high degree of commercial confidence and defensive IP intent.

International Business Machines Corporation (IBM) is the second major industrial assignee, with patents from 2020 and 2024 directed specifically at trench-based metal filling techniques in nanosheet source/drain regions to mitigate contact resistance from material overfill effects. IBM’s approach is complementary to Applied Materials’ process integration strategy, addressing a distinct failure mode — overfill-induced resistance — rather than the fundamental barrier height problem.

Acorn Technologies, Inc. occupies a unique position as the long-standing IP holder for Fermi-level depinning at metal-semiconductor junctions. Their portfolio extends from the foundational 2005 US and Taiwan patents on ultra-thin interfacial layers through to a 2022 Taiwan patent on group III/V atomic monolayer insertion for group IV semiconductors. This 17-year IP continuity represents a significant barrier to freedom-to-operate for any process flow that relies on interfacial depinning.

Academic contributions shaping the technology roadmap

On the academic side, RWTH Aachen University (Germany) and National Taiwan University have made fundamental contributions to understanding Fermi-level depinning and low-work-function ohmic contacts. Xidian University (China) has contributed process-level research on ZnO-based interfacial engineering for Ge-channel devices. Chungbuk National University (Korea) has published on n-type nanosheet FET fabrication process simplification. The research trend across 2018–2024 shows a convergence toward combined approaches: process-integrated silicidation for bulk Si nanosheet FETs, while emerging 2D-material nanosheet research focuses on BN and graphene interlayer insertion informed by density functional theory (DFT) calculations — a methodology endorsed by leading computational materials science journals including those indexed by APS.

• Applied Materials, Inc. — dominant assignee; US, WO, KR, JP, CN, TW filings (2022–2024); selective silicidation + full-stack metal fill process integration
• IBM — second major assignee; US filings (2020, 2024); trench-based metal fill to mitigate overfill-induced contact resistance
• Acorn Technologies, Inc. — consistent FLP depinning portfolio since 2005; US and TW filings; ultra-thin interfacial layers and group III/V atomic monolayer insertion
• RWTH Aachen University — silicon nitride interface engineering for Fermi-level depinning; Al + SiN achieving 0.2 eV SBH to Si conduction band
• Xidian University — ZnO/Ar plasma interfacial engineering for n-Ge contacts; ohmic contact at 3×10¹⁶ cm⁻³ doping
• University of Twente — computational demonstration of BN monolayer reducing effective metal work function by up to 2 eV for MoS₂ contacts
• IHPC Singapore — experimental Ni-graphene electrodes achieving 200 Ω·µm contact resistance on MoS₂

The dataset of approximately 60 patent filings and literature entries spanning 2000–2024 reviewed for this analysis is accessible and searchable via PatSnap’s innovation intelligence platform, which aggregates global patent databases alongside scientific literature for cross-domain prior art and landscape analysis.