Why CPO eliminates the biggest source of transceiver power waste
Co-packaged optics reduces AI chip power consumption primarily by removing the long electrical interconnect between the switch ASIC and the optical transceiver — the single largest source of signal degradation and compensatory power overhead in traditional pluggable architectures. In conventional designs, high-speed electrical signals travel from the switch ASIC across a PCB, through a connector, and into a pluggable module. That path introduces significant insertion loss, and recovering signal integrity requires power-hungry re-timers, CDR (clock-data-recovery) circuits, and DSP components.
As stated explicitly in Alibaba’s 2022 patent Flexible Switching Solution Based on Co-Packaged Optics, CPO technology “allows optical modules to be co-packaged with the switch ASIC, thereby significantly reducing the length of switch-to-optical interconnects and reducing the power consumption of the switch’s electronic I/O.” The same filing notes that CPO-based switches “can provide a low-power and low-cost alternative to pluggable optical transceivers in large data centers.”
By eliminating DSP and CDR devices, CPO and LPO architectures save approximately 50% of module power consumption compared to traditional pluggable transceivers, according to Hangzhou Kaimu Photonics’ 2025 patent Co-Packaged Optical Engine Module and Networking.
Hangzhou Kaimu Photonics’ 2025 patent quantifies the benefit directly: eliminating DSP and CDR devices means CPO and LPO architectures “save approximately 50% of module power consumption” relative to traditional pluggable transceivers. The same patent notes that the CPO approach “co-packages the optical engine and ASIC chip onto the same substrate, achieving improved electrical I/O and optical I/O bandwidth while reducing losses.”
Juniper Networks’ 2022 patent Power-Efficient and Scalable Co-Packaged Optical Devices adds an important dimension: by using spectrally efficient signalling formats such as QAM-64 and PAM-8 on the short, tightly integrated electrical traces within a CPO package, the ASIC can handle higher data rates “without adding additional data lines and without significantly increasing the design’s power consumption.” This is the core power-bandwidth tradeoff that CPO makes possible — higher spectral efficiency per watt on interconnects that are centimetres rather than tens of centimetres long, a principle well-documented by IEEE in photonic integration research.
CPO is a packaging architecture that places optical transceiver modules on the same substrate as the switch or AI ASIC, eliminating the PCB traces, connectors, and pluggable module housing of traditional transceiver designs. By shortening the electrical path between chip and optics to millimetres, CPO removes the signal integrity overhead — re-timers, CDR, and DSP circuits — that consumes significant power in pluggable architectures.
3D stacking and heterogeneous integration: minimising parasitic loss
3D stacking of photonic and electronic integrated circuits directly adjacent to the ASIC is the primary architectural strategy for reducing interconnect length, parasitic inductance, and signal distortion in advanced CPO implementations. Beyond simply co-locating the optical module and ASIC on the same PCB, 3D stacking places the photonic integrated circuit (PIC), driver/TIA electronic integrated circuit (EIC), and processing layer in a vertical sequence measured in microns rather than millimetres.
HG Genuinelight Rockley Technology’s 2021 patent High-Density CPO Silicon Photonics Engine describes a 3D solid packaging architecture that stacks an electrical chip assembly — comprising driver chips and TIA chips in vertical sequence — directly atop the optical chip, which is seated in a recess of the circuit substrate. The filing reports this approach “doubles the transmission bandwidth of the CPO silicon photonics engine” and “solves the problems of insufficient space for the electrical chip assembly in 2D packaging technology, high-frequency signal distortion caused by the connection method of opto-electronic chips, and low bandwidth.” Eliminating the longer lateral routing paths of 2D layouts directly reduces the parasitic inductance and capacitance that degrade high-frequency signal fidelity and force higher drive power.
HG Genuinelight Rockley Technology’s 3D CPO silicon photonics engine, described in a 2021 patent, doubles transmission bandwidth by stacking driver and TIA chips vertically atop the optical chip, eliminating 2D lateral routing paths that cause high-frequency signal distortion.
II-VI Delaware (Coherent)’s 2025 patent 3D Co-Packaged Optics Stack formalises this concept into a defined layer sequence: a thermal management and control layer, a PCB layer, a processing layer, a TIA/Driver EIC layer, and a PIC layer — each positioned so that the PIC is adjacent to the driver/TIA, which is adjacent to the processing (ASIC) layer. The thermal management layer sits at the top, enabling direct heat extraction from the processing layer. This matters for power efficiency: without managed heat extraction, ASICs throttle their operating frequency at high power loads, reducing effective throughput. Standards bodies including IEEE and industry groups tracked by ITU have highlighted thermal management as a primary constraint in next-generation optical interconnect scaling.
“By eliminating DSP and CDR devices, CPO and LPO architectures save approximately 50% of module power consumption compared to traditional pluggable transceivers.”
ASE Advanced Technology Research (Kunshan)’s 2026 patent CPO Heterogeneous Integration Packaging Structure and Manufacturing Method employs 2.5D/3D integration, stacking the photonic engine chip — comprising EIC and PIC bonded via flip-chip onto an interposer — alongside the custom ASIC on a shared interposer with vertical through-holes. The filing states this approach “significantly improves integration density and reduces power consumption” by shortening the distance between the photonic engine chip and the electronic chip, while also delivering “good electrothermal performance.”
Hangzhou Kaimu Photonics’ 2025 patent takes heterogeneous integration further by eliminating the silicon interposer, organic package, and intermediate PCB substrates entirely, stacking the PIC directly onto the processor die. The inventors argue this “further shortens the transmission path, improves data transmission efficiency” and “significantly reduces signal loss, improving high-speed signal integrity” — all of which translate into lower required transmit power and reduced error correction overhead.
Explore the full patent landscape for CPO packaging architectures and 3D photonic integration.
Analyse CPO Patents in PatSnap Eureka →Optical coupling efficiency and its direct link to laser power draw
Coupling loss at the laser-to-PIC interface is a significant and often underestimated source of power overhead in CPO systems. Every decibel of coupling loss requires higher laser drive power to maintain the optical power budget, directly increasing total system power consumption. As CPO packaging becomes more complex — with multiple interposer layers and bump interconnects between the laser diode and the PIC — maintaining coupling efficiency becomes a distinct engineering challenge.
Xun Yun Electronic Technology (Zhongshan)’s 2024 patent Vertically Coupled CPO Optical Engine Packaging Structure addresses this by introducing a vertical coupling geometry. A silicon photonic chip is mounted on a substrate with diffraction gratings fabricated on its surface; a lens array is positioned between the fibre array and the gratings to form a vertical coupling path. This design integrates the ASIC for network data processing, the silicon photonic chip for signal conversion, and the electronic chip for photoelectric signal conversion in a single compact structure. The vertical coupling geometry reduces the footprint and enables tighter ASIC integration, directly reducing the electrical path length from chip to transceiver.
Wuxi Xinguang Interconnect Technology Research Institute’s 2024 patent on light source systems for CPO optical modules develops a two-lens collimation system to solve the coupling loss problem caused by the inability to achieve co-substrate connection between the PIC and laser diode in advanced packaging configurations with multiple interposer layers.
Wuxi Xinguang Interconnect Technology Research Institute’s 2024 patent Light Source System for Advanced Packaging CPO Optical Modules and Assembly Method tackles the same problem from the laser side. Because the PIC and laser diode cannot share a common substrate in advanced packaging configurations — due to multiple interposer and bump layers between them — the inventors develop a two-lens system to collimate and then focus the laser beam into the PIC’s optical I/O ports. This provides “larger coupling tolerance” and solves the “light loss problem caused by the inability to achieve co-substrate connection between the PIC and LD.” As research published by Nature Photonics has documented, coupling loss in silicon photonic systems is one of the primary barriers to achieving the power efficiency gains that photonic integration theoretically enables.
Cisco’s 2024 patent Power and Optical Integration via Cold Plate for Delivery to Electronic and Photonic Integrated Circuits approaches the thermal-power coupling problem at the system level. As ASIC process nodes advance and device power increases, delivering power to the ASIC introduces additional thermal challenges that can throttle operating frequency. Cisco routes both power and optical signals through cold plates — liquid cooling structures — that sandwich the substrate and die package, with power vias and optical paths integrated directly into the cold plate. This co-integration of thermal management with signal delivery addresses the thermal bottleneck that limits CPO ASIC clock speeds and effective throughput.
As ASIC power density increases with each process node, thermal throttling — not raw electrical efficiency — becomes the binding constraint on CPO system throughput. Both II-VI Delaware’s 3D stack and Cisco’s cold-plate integration patent address this by making thermal management an integral part of the CPO package architecture, not an afterthought.
Wuxi Xinguang Interconnect Technology Research Institute’s 2026 patent Optical Engine Based on CPO Technology describes a complete CPO optical engine integrating TIA chips, PIC chips, and driver chips in separate transmit and receive modules arrayed on a PCB, with the assembly interfacing to external electronics via socket pads on the PCB back surface. The filing specifically notes that this architecture achieves “small size, low performance loss, low power consumption, and high reliability,” and addresses the challenge that traditional pluggable optical modules face increasing heat, reliability, and crowding problems as speeds increase — a concern also flagged in ITU standardisation work on next-generation optical access networks.
System-level optimisation: balancing loads across optical and electrical paths
System-level photonic-electronic interconnect optimisation — dynamically balancing computational and communication loads across optical and electrical paths based on measured energy efficiency ratios — represents a firmware-level approach to CPO power management that is only possible because CPO places optical interconnects at the chip package level, making their power characteristics directly observable and controllable.
Zhi’anzhe Information Technology (Suzhou)’s 2025 patent Optimization Method and System for Multi-Chip Photonic-Electronic Hybrid Interconnects proposes an optimisation framework that calculates an “overall photonic-electronic interconnect transmission energy efficiency ratio” incorporating optical interconnect power data, electrical interconnect power data, optical wavelength multiplexing factors, and optical channel capacity for each chip. When the energy efficiency ratio exceeds a preset threshold, an optimisation model is invoked to determine the best distribution of computational and communication loads across chips, “ensuring the system operates at high energy efficiency, reducing unnecessary power consumption, and lowering operating costs.”
Suzhou Qidian Photonic Intelligence Technology’s 2025 patent OIO Chiplets and AI Computing Clusters addresses GPU-to-GPU scale-up interconnect using an OIO (Optical I/O) chiplet that packages an optical chip, electronic chip, and microcontroller into a single unit. Compared to copper cable interconnects, this “greatly increases interconnection distance and expands the scale of GPU scale-up networks.” Compared to existing optical module solutions, it offers “low latency, low power consumption, high bandwidth density, and high reliability.” The key power advantage is the elimination of high-power SerDes (serializer/deserializer) circuits required in copper-based or traditional optical module interconnects for long-distance signal conditioning — a significant overhead in large AI training clusters.
Zhi’anzhe Information Technology (Suzhou)’s 2025 patent proposes a system-level optimisation framework that calculates a photonic-electronic interconnect transmission energy efficiency ratio and invokes an optimisation model when the ratio exceeds a preset threshold, dynamically redistributing computational and communication loads to reduce unnecessary power consumption across multi-chip AI clusters.
Intel’s 2024 patent Optical Packaging Using In-Mold Embedded (EIM) Optical Module Integration addresses the manufacturability dimension of CPO for AI applications. Intel’s approach embeds the EIC, PIC, and pluggable optical coupling connector into a moulded compound, creating a module-level unit that reduces packaging complexity and enables the small form factors required for “co-packaged optical systems (CPO), AI, CPU-to-CPU (memory) optical interconnects, autonomous vehicles, mobile devices, wearable devices” — all of which require “high bandwidth and bandwidth density” while maintaining power efficiency. The WIPO global patent database shows CPO-related filings have accelerated sharply since 2021, reflecting the convergence of AI cluster scaling requirements with photonic manufacturing maturity.
Track CPO patent filings across jurisdictions and monitor competitor innovation in photonic-electronic integration.
Explore Full Patent Data in PatSnap Eureka →Key patent holders and the innovation landscape
Chinese institutions dominate the volume of CPO-specific filings in the patent dataset analysed. Wuxi Xinguang Interconnect Technology Research Institute holds multiple patents covering CPO optical engine integration and laser coupling solutions. HG Genuinelight Rockley Technology holds the high-density 3D CPO silicon photonics engine patent. Hangzhou Kaimu Photonics addresses the elimination of intermediate substrates. Xun Yun Electronic Technology (Zhongshan) covers vertical coupling architectures. These Chinese filers reflect the rapid buildout of domestic CPO supply chains aligned with AI chip manufacturing.
Among US and international assignees, II-VI Delaware (Coherent) holds the formalised 3D CPO stack patent covering the full layer sequence from thermal management through PIC. Juniper Networks holds the power-efficient scalable CPO patent addressing spectral efficiency and ASIC integration. Cisco holds the cold-plate power and optical integration patent for high-power ASIC environments. Alibaba holds the flexible CPO switching solution patent addressing DR and FR connectivity standards. Intel holds the EIM optical module integration patent addressing manufacturability for AI and HPC applications. Luxtera (now part of Cisco) holds an earlier photonic interposer patent from 2013 that represents foundational prior art for CPO architectures, demonstrating CMOS electronic die integration with silicon photonic interposers.
A secondary innovation trend — photonic computing — is represented by Celestial AI, whose coherent photonic computing architecture patents (Korean and Japanese jurisdictions, 2023–2024) describe using photonic crossbar circuits to implement neural network linear algebra operations optically, with WDM enabling efficient specific network model implementation. While not strictly CPO in the switching sense, this represents the extension of photonic integration logic into the AI compute fabric itself, a direction also being monitored by standards bodies including IEEE.
The dataset of approximately 15 directly relevant patent sources spans filings from Chinese, US, Korean, and other jurisdictions, covering CPO packaging architectures, photonic-electronic integration strategies, and AI chip power optimisation through optical interconnects. The dominant technical approaches include 3D stacking of PICs and EICs on shared substrates, elimination of DSP/CDR components, wavelength division multiplexing (WDM) for bandwidth scaling, and integration of TIA/driver chiplets in close proximity to switching ASICs. Patent data from PatSnap’s innovation intelligence platform enables tracking of these filings across jurisdictions in real time.
“Spectrally efficient signalling formats such as QAM-64 and PAM-8 on short CPO electrical interfaces allow higher bandwidth without proportional power increases — the core power-bandwidth tradeoff that CPO makes possible.”