How DBC and AMB substrates are actually bonded

Direct Bonded Copper (DBC) and Active Metal Brazing (AMB) substrates both deliver the ceramic insulator / copper conductor laminate that SiC power modules require — but they achieve that bond through fundamentally different chemistry, at different temperatures, and with different consequences for what ceramics can be used. DBC exploits the Cu–Cu₂O eutectic reaction at approximately 1065 °C: no braze alloy is needed, and the copper bonds directly to the ceramic surface. AMB, by contrast, uses a braze alloy containing an active metal — most commonly titanium (Ti), zirconium (Zr), or hafnium (Hf) — in a Cu–Ag–Ti or Cu–P–Ti system that reacts chemically with the ceramic at 800–900 °C, forming a stable metallurgical bond even on ceramics that molten metal would not normally wet.

The DBC process is manufacturing-mature and widely industrialised. Standard semiconductor-grade copper foil is bonded to alumina (Al₂O₃) or aluminum nitride (AlN) ceramic, and the resulting three-layer sandwich is then wet-etched to form circuit traces. This process compatibility with existing semiconductor fabs is a significant commercial asset. As documented across dozens of Chinese and international patent filings — including State Grid Shanghai’s double-sided cooling SiC module (2024) and Xi’an Jiaotong University’s 1000 A half-bridge module (2022) — DBC remains the default substrate for general-purpose SiC packaging.

AMB’s active-metal braze chemistry is inherently more complex. It requires vacuum or inert-atmosphere brazing, precise alloy composition control, and specialised equipment. Mitsubishi Materials’ US patent (2019) reveals that the filler metal melting point must be 710 °C or lower to enable simultaneous co-sintering with the active metal, demanding careful alloy design. This manufacturing complexity translates directly into higher substrate unit cost compared to standard DBC — but it also unlocks ceramic options that are inaccessible to DBC, as the next section explains.

Why ceramic choice defines SiC reliability

The ceramic layer in a power module substrate is not merely an electrical insulator — it is the primary determinant of thermal management performance and long-term mechanical reliability. For SiC modules specifically, the mismatch between the ceramic’s coefficient of thermal expansion (CTE) and that of the SiC chip is the dominant failure mechanism under power cycling. SiC chips have a CTE of approximately 4 ppm/K. Copper is approximately 17 ppm/K. Alumina (Al₂O₃) — the most common DBC ceramic — is approximately 7 ppm/K. Under repeated thermal excursions, this mismatch generates stress concentrations at the copper–ceramic interface that propagate cracks through the ceramic or delaminate the copper layer.

AlN ceramic — available in both DBC and AMB — offers a CTE of approximately 4.5 ppm/K and a thermal conductivity of approximately 170 W/(m·K), making it the superior DBC ceramic choice for SiC. State Grid Shanghai’s 2024 double-sided cooling SiC module patent explicitly specifies AlN as the ceramic material precisely for its higher thermal conductivity. However, the real breakthrough enabled by AMB is access to silicon nitride (Si₃N₄). Si₃N₄ has a CTE of approximately 3.2 ppm/K — the closest match to SiC at ~4 ppm/K among industrially available ceramics — a fracture toughness of approximately 6–7 MPa·m^(1/2) (roughly 3–4 times higher than Al₂O₃ and approximately 1.5 times higher than AlN), and a thermal conductivity of approximately 70–90 W/(m·K). Conventional DBC cannot bond reliably to Si₃N₄ due to the ceramic’s low surface reactivity; AMB’s active titanium chemistry overcomes this barrier.

“Si₃N₄ has a fracture toughness of approximately 6–7 MPa·m^(1/2) — roughly 3–4 times higher than Al₂O₃ — combined with a CTE of approximately 3.2 ppm/K, which is closely matched to SiC at 4 ppm/K. This near-CTE-match is transformative for long-term reliability under thermal cycling.”

Mitsubishi Materials has directly quantified the reliability benefit. Their JP 2016 patent demonstrates that an optimised AMB substrate with an Ag-Cu eutectic interfacial layer controlled to ≤14 μm shows no ceramic cracking after 3,500 thermal cycles from −45 °C to 150 °C — a standard automotive qualification criterion. By contrast, standard DBC with Al₂O₃ shows crack initiation at significantly lower cycle counts at these temperature extremes. According to IEEE, power cycling reliability is increasingly the binding constraint for next-generation SiC inverter qualification, making this gap material for automotive and industrial designers.

The DBC CTE mismatch problem has become a recognised design constraint. Hebei University of Technology’s 2025 patent explicitly identifies DBC CTE mismatch as a key unsolved reliability problem, motivating an alternative Insulating Metal Baseplate (IMB) architecture that replaces the DBC ceramic with an insulating resin layer matched in CTE to copper. Shandong University’s 2024 patent goes further, proposing a semi-insulating SiC single-crystal double-copper-clad substrate — where the ceramic itself is SiC — to bring the substrate CTE into near-perfect alignment with the SiC chip. These emerging approaches underscore that the thermal cycling reliability of DBC/Al₂O₃ is a genuine engineering limitation, not merely a theoretical concern.

The engineered interfacial chemistry of AMB

AMB’s reliability advantage is not simply a consequence of using better ceramics — it flows from a precisely engineered multilayer interface at the copper–ceramic junction that provides both chemical adhesion and mechanical compliance under thermal stress. Mitsubishi Materials’ EP 2021 patent describes the AMB Cu–ceramic joint as containing three distinct layers: a Cu–Sn layer close to the ceramic surface, a first intermetallic compound layer of Cu–Ti, and a second intermetallic compound layer containing P and Ti. Each layer plays a specific role: the Cu–Sn layer provides chemical bonding to the ceramic; the Cu–Ti intermetallic anchors the copper member; and the P–Ti phase provides mechanical compliance to absorb differential thermal expansion.

This structured interface is not a manufacturing artefact — it is deliberately engineered. Mitsubishi Materials’ US patents (2016, 2018) disclose a Cu–P–Ti brazing filler system containing 3–10 mass% P and an active Ti material that, when heated, forms the sequence of intermetallic layers described above. The Cu–Sn layer on the ceramic side contains Sn in solid solution; the Ti-based intermetallic on the Cu member side provides strong adhesion; the P–Ti second phase sits between them providing compliance. Mitsubishi’s research, cited by Nature-indexed materials journals, establishes that controlling the thickness of the Ag-Cu eutectic layer to ≤14 μm at the interface is the key process variable for achieving 3,500-cycle thermal fatigue life.

The DBC interface, by comparison, relies on a simpler Cu₂O-assisted eutectic reaction producing a relatively direct Cu-to-ceramic bond. Mitsubishi Materials’ JP 2013 patent reveals that introducing controlled Cu concentrations of 0.05–5 wt% at the ceramic-metal junction interface can improve heat cycle performance in DBC — but this remains a refinement of a fundamentally simpler interface, not the engineered multilayer compliance mechanism of AMB. The practical consequence is that DBC interfaces are more susceptible to crack propagation under the extreme junction temperatures (above 300 °C) that SiC devices can sustain, as noted in the Korean OBC module patent (2020).

Zhuhai Wodeke Technology’s 2025 patent describes an alternative AMB fabrication route that further reduces thermal stress during processing: a Ti-Cu transition layer is first sputter-deposited onto the Si₃N₄ substrate by vacuum sputtering, followed by lamination of high-purity oxygen-free copper foil, then ultrasonic-assisted annealing to relieve residual stress. The patent notes this method “can complete the welding process at relatively low temperatures, reduce thermal stress damage, while ensuring high electrical conductivity and thermal conductivity” — an important process innovation for volume manufacturing of AMB/Si₃N₄ substrates.

Where each substrate wins: applications and trade-offs

DBC and AMB substrates are not strictly competing technologies — they occupy different positions within the SiC module performance-cost spectrum, and patent evidence shows they are increasingly used together within the same module as different functional components. Understanding which substrate wins in which application requires mapping technical attributes to operating requirements.

DBC with Al₂O₃ or AlN ceramic dominates general-purpose SiC applications where cost efficiency and manufacturing scalability are primary constraints. NIO Power Technology’s 2022 patent employs stacked DBC substrates for a multi-chip SiC half-bridge module targeting EV drive applications. Xi’an Jiaotong University’s 2022 patent uses three parallel DBC sub-units to build a 1000 A half-bridge module, with SiC MOSFET chips soldered to DBC surfaces in a nitrogen atmosphere. Guangdong Power Grid Research Institute’s 2024 patent adopts DBC ceramic substrates for a 3.3 kV / 2000 A single-switch SiC module targeting rail transit traction and HVDC flexible transmission — applications where current capacity and manufacturability are prioritised over ultimate thermal fatigue life. Standards bodies including IEC and IEEE continue to reference DBC as the baseline substrate technology in power module qualification standards.

AMB substrates are favoured where maximum reliability under severe thermal cycling or highest junction temperatures is the governing requirement. Cree’s (now Wolfspeed) flagship AMB-based SiC module patents explicitly target high-frequency converters where switching losses and thermal stress are most intense. The Cree US 2020 patent states: “By using an AMB substrate with an aluminum nitride base layer, the thermal dissipation characteristics of the power converter module may be substantially improved while maintaining the structural integrity of the power converter module.” The same patent specifies that the AMB substrate enables the module’s switching path length to be kept below 50 mm and gate control path length below 20 mm — minimising stray inductance while the AMB/AlN structure handles the resulting high thermal loads.

Guilin University of Electronic Technology’s 2025 patent illustrates a further AMB advantage: in a copper-clip-interconnected SiC module, the AMB substrate reduces source-side parasitic inductance, provides an additional thermal path from chip source to the copper layer, reduces surface stress on the chip source terminal, and improves interconnect reliability — benefits that flow directly from the higher mechanical strength of the AMB/Si₃N₄ substrate system.

The most striking finding from the patent landscape is that DBC and AMB are increasingly used together in the same module. Huawei Technologies’ 2025 dual-sided cooling power package patent explicitly states that both AMB and DBC (DCB) materials are used as busbar elements within the same molded power package, noting: “AMB and DCB materials are superior because thin layers (e.g., 320 μm) can already ensure necessary isolation robustness. Moreover, ceramics have a more favorable relative permittivity compared to molding compounds.” This complementary deployment — DBC for cost-sensitive carrier substrates, AMB for high-stress busbar or chip-carrier positions — may become the dominant packaging architecture for next-generation SiC modules.

Head-to-head: DBC vs AMB at a glance

The following comparison synthesises the key technical parameters from the patent and literature evidence surveyed, covering more than 50 sources across Chinese, US, European, Japanese, Korean, and PCT filings. The dominant assignees contributing substrate-technology disclosures include Mitsubishi Materials Corporation, Cree Inc. (now Wolfspeed), Infineon Technologies AG, Huazhong University of Science and Technology, Xi’an Jiaotong University, Xidian University, and Chongqing University.

The patent evidence makes clear that substrate selection for SiC power modules is not a binary choice between DBC and AMB — it is a multi-variable optimisation across cost, manufacturing readiness, thermal performance, and reliability target. For high-volume, cost-sensitive EV and industrial applications, DBC with AlN ceramic remains the pragmatic choice. For high-frequency converters, automotive traction inverters operating at extreme junction temperatures, and any application where long-term power cycling reliability is the binding constraint, AMB with Si₃N₄ or AlN ceramic provides a demonstrably superior substrate platform. As WIPO patent filing trends indicate, the volume of AMB-related SiC substrate disclosures has grown substantially since 2020, reflecting the technology’s maturation from laboratory demonstration to commercial deployment.

“AMB and DCB materials are superior because thin layers (e.g., 320 μm) can already ensure necessary isolation robustness. Moreover, ceramics have a more favorable relative permittivity compared to molding compounds.” — Huawei Technologies, 2025

The emergence of hybrid module architectures — using both DBC and AMB as different functional components within the same package — suggests the industry is converging on a complementary deployment model rather than a winner-takes-all substrate transition. Designers who understand the precise mechanical, thermal, and chemical differences between these two bonding technologies will be best positioned to make the substrate selection that maximises module reliability at the lowest system cost.