Core Architecture: Constructing the Semiconductor Fab Digital Twin

A semiconductor fab digital twin is a multi-layered virtual replica of the physical manufacturing environment, synchronized in real time with equipment sensor data, process parameters, and metrology measurements. The basic construction flow involves three sequential layers: establishing equipment interaction models, building process-domain representations, and continuously calibrating those representations against real fab outcomes.

The most detailed process-centric digital twin architecture for semiconductor quality prediction is disclosed by Jiangsu Mengxing Intelligent Technology (2023). Their end-to-end pipeline first collects raw material dimension and attribute data to build a semiconductor raw material feature set, then constructs an initial digital twin model by reading equipment model information to form device interaction constraints. Sequential temporal features are extracted from equipment processing history, and these features are used to execute model personalization configuration. A sample set is generated by partitioning the raw material distribution space into regions with centroid identifiers, and controlled simulation runs produce feature compensation vectors that iteratively optimize the initial model until processing quality prediction accuracy converges.

A closely aligned hybrid approach from Shanghai Xingyuan Innovation Center (2025) constructs the chip digital twin by first performing physical simulation on an ideal process flow to obtain a physics-based prediction model, then training a residual correction model on actual measured data. This architecture is significant because the machine learning component needs only to learn the low-magnitude residual mapping of process deviations, dramatically reducing model complexity and improving prediction accuracy. When final predicted values exceed defined thresholds, the system issues anomaly alerts and classifies chips into performance grades.

For equipment-level construction, Lam Research Corporation (2023) describes a process chamber digital twin consisting of spatially coupled sub-models. Each sub-model can be an AI/ML model, a high-fidelity simulation (HFS) model, or a closed-form solution, and each generates outputs covering thermal properties, plasma properties, fluid dynamics, and structural properties. The coupling of first-location and second-location models within the chamber creates a spatially resolved digital representation that can be updated as chamber conditions drift — a critical requirement for long-running production environments where chamber aging is continuous.

Yield Prediction Models: From Virtual Metrology to In-Fab Wafer Forecasting

Yield prediction within the digital twin framework requires translating real-time process data and equipment state into estimated device performance metrics. The patent literature reveals a spectrum of approaches ranging from virtual metrology of individual process steps to full-wafer path simulation — and the most advanced implementations chain all of these layers together into a single closed-loop system.

Samsung’s Virtual Process Path Approach

Samsung Electronics has filed the most targeted patents on in-fab wafer yield prediction. A 2025 EP patent discloses a system that generates virtual process paths for wafers still in production, then uses a trained yield prediction model to predict the final yield of virtual “fab-out” wafers corresponding to each path. A path-generating model is trained on wafer data from actual completed process paths, and embeddings of wafer data serve as model inputs. Because multiple virtual paths can be generated per in-fab wafer, the yield distribution across those paths allows engineers to identify process scheduling risks before fabrication is complete. The Chinese-language equivalent clarifies that semiconductor manufacturing steps include oxidation, lithography, etching, deposition, ion implantation, and metal interconnection, and that critical dimension (CD) measurement after specific steps provides the linking measurement to the yield model.

LSTM-Based Virtual Metrology for Temporal Drift

Shanghai Huali Integrated Circuit Manufacturing (2022) addresses one of the most persistent problems in fab digital twins: gradual equipment degradation that causes static models to drift out of accuracy. Their solution is a dual-module LSTM architecture in which a base LSTM predicts measurement parameters from tool data, while a sliding-window LSTM continuously updates model parameters by capturing long-term drift in process variables and measurement data. The sliding window incorporates FDC data and the measured data from the preceding three to five wafers, enabling the system to adapt to gradual equipment degradation across different process chambers and time periods. According to IEEE standards for industrial machine learning, temporal adaptation mechanisms of this kind are considered essential for production-grade predictive maintenance systems.

“Yield — rather than process parameter error — should be the primary optimization target, because minimizing process parameter errors can inadvertently degrade yield on individual dies.”

ASML’s Geometric-Parameter Yield Abstraction

ASML Netherlands B.V. approaches yield prediction through a geometric-parameter abstraction layer. In patents filed in the US (2022) and China (2024), a trained first model translates modeled geometric parameters — device element dimensions and positions as manufactured by the process — and trained free parameters into a yield parameter. Process parameter data is converted into geometric parameter values, and the yield parameter is predicted from that geometry. The core argument, consistent with principles endorsed by WIPO in its technology trend reports on semiconductor manufacturing, is that yield should be the direct optimization target rather than an indirect proxy like process parameter error.

Neural Network Plus Monte Carlo for IC Yield

Samsung Electronics also discloses a neural-network-plus-Monte-Carlo architecture (KR, 2023): the processor receives operational characteristic variables, performs simulation, applies neural network regression analysis to determine a functional relationship for those variables, then uses an advanced Monte Carlo simulation seeded with that function to predict yield across the full distribution of process variation. This approach is particularly well-suited to capturing the stochastic nature of defect formation at advanced process nodes.

Closed-Loop VM-to-WAT Pipeline

Excore Holdings (2025) demonstrates a virtual metrology layer feeding an inline-to-WAT (Wafer Acceptance Test) prediction pipeline. Real-time FDC data from process tools is input to a VM model that predicts inline measurement parameters. Those inline parameters are then fed to an Inline-WAT prediction model, which outputs predicted WAT values using a recursive feature selection method combined with cross-validation. When predicted WAT values breach anomaly control limits, process corrections are automatically dispatched to both the current station and downstream stations — closing the loop between process control and final electrical performance.

Process Simulation Calibration and Spatial Modeling

Yield prediction accuracy is bounded by the fidelity of the underlying process simulation models. The digital twin must be continuously calibrated against real metrology data to remain predictive as process conditions shift — and the patent literature identifies two primary calibration mechanisms: CD-SEM-driven cost function optimization and spatial ML models built from combined metrology data sources.

Lam Research’s CD-SEM Calibration Family

Lam Research Corporation holds a family of patents on process simulation model calibration using CD-SEM. Patents filed across South Korea (2020, 2025) and China (2020) collectively define a method where cost values are generated from computationally predicted semiconductor manufacturing outcomes combined with metrology results from reaction chamber operations under fixed process parameters. Pre-process profiles are provided as inputs to the simulation model, and post-process profiles are optimized against measured profiles. Cost functions for optical scatterometry, SEM, and TEM are used to steer the optimization, enabling the simulation model to be calibrated without requiring destructive characterization of every wafer. This approach aligns with calibration frameworks recommended by NIST for advanced manufacturing metrology.

Applied Materials’ Spatial Digital DoE

Applied Materials extends calibration to spatial modeling. Patents filed in China (2023 and 2024) describe building a spatial prediction model by combining virtual metrology data from equipment sensors, on-board metrology (OBM) data from device structures on the wafer, and precision SEM in-line metrology data. A machine learning engine refines an empirical process model using this combined custom metrology data, outputting spatial maps of dimensions of interest across the wafer. The resulting model supports digital Design of Experiments (digital DoE) that can predict process outcomes across multi-dimensional parameter spaces without physically processing additional wafers, and enables multi-constraint optimization for each processing tool.

ASML’s Hybrid Tuning Loop for Lithography

For lithographic process monitoring, ASML Netherlands B.V.’s 2025 KR patent describes receiving substrate geometry signals from a manufacturing process, using a machine learning predictive model to predict output substrate geometry, and tuning that prediction by comparing against physical substrate measurements and predictions from physics-based models. This hybrid tuning loop maintains prediction accuracy as lithographic tool conditions drift — a persistent challenge in high-volume manufacturing environments documented by the EPO in its semiconductor technology trend reports.

Samsung’s RNN-Based Sequential Process Simulation

Samsung Electronics’ RNN-based semiconductor process simulation system (KR, 2021) implements a recurrent neural network consisting of time-series-arranged process emulation cells. Each cell receives the previous output profile and the target profile and process condition for the current step, using prior knowledge of time-series causal relationships to generate the current step output profile. This RNN architecture is a natural fit for the sequential, causally ordered nature of semiconductor manufacturing, where each process step’s output becomes the input state for the next.

Key Players and Innovation Trends Across the Patent Landscape

The patent data reveals distinct strategic clusters among leading assignees, with each major player concentrating on a different layer of the digital twin stack. The dataset encompasses more than 50 patent records spanning South Korea, China, the United States, Europe, Japan, and Australia — making it one of the most geographically diverse technology areas in semiconductor process innovation.

Samsung Electronics: End-to-End Yield Intelligence

Samsung Electronics is the most prolific assignee in direct semiconductor yield prediction. Its filings span in-fab virtual process path generation and yield forecasting, neural network regression combined with Monte Carlo simulation for IC yield, FDC-based machine learning for chamber-level virtual wafer generation, and semiconductor process modeling via tensor-preprocessed data inputs (KR, 2023 and 2024). Samsung’s approach is notably end-to-end: from physical chamber FDC values through virtual wafer generation to final yield probability — a comprehensive stack that few other assignees attempt to cover in a single patent family.

Lam Research: Calibration and Model-Based Scheduling

Lam Research Corporation focuses on the calibration layer of the digital twin — ensuring that process simulation models stay synchronized with real chamber physics through CD-SEM-driven optimization — as well as model-based scheduling. A 2024 JP patent uses nested neural networks trained on preventive maintenance data, recipe times, and wafer-less automated cleaning times to predict optimal scheduling parameters and maximize tool utilization.

Applied Materials: Spatial Process Control

Applied Materials concentrates on spatial digital DoE and adaptive process control, combining OBM, VM, and precision SEM data to build wafer-level spatial prediction models. Its pair of CN-jurisdiction patents from 2023 and 2024 establish a framework for multi-constraint optimization that operates at the spatial granularity of individual wafer locations — a level of resolution that conventional process control approaches cannot match.

ASML: Yield-Targeted Lithographic Control

ASML Netherlands B.V. holds patents on yield-targeted process control, arguing that metrology and control should optimize yield directly rather than process parameter errors. Its 2022 KR patent establishes an early framework for ML-based substrate geometry prediction and tuning, which the 2025 KR filing extends with a more complete hybrid tuning loop.

Chinese Semiconductor Firms: Rapidly Growing Cluster

Chinese semiconductor companies represent an emerging and rapidly growing cluster within this patent space. United Microelectronics (联华电子) files semiconductor process prediction methods using heterogeneous data from multiple neural network branches (CN, 2022) and confidence-threshold-triggered model self-correction (CN, 2023). Shanghai Huali focuses on LSTM-based virtual metrology. Excore Holdings builds full closed-loop systems integrating VM and WAT prediction. Shanghai Jita Semiconductor applies machine learning to optimal process parameter prediction (CN, 2025). Korea Electronics and Telecommunications Research Institute (ETRI, 2025) contributes a real-time digital twin agent framework in which learning models are mapped to digital twin objects representing manufacturing resources and updated via a twin agent in real time.