Static Refresh: Fixed-Rate Operation and Its Structural Limits

Static refresh issues a refresh command at a predetermined fixed interval — defined by the JEDEC tREFI window (typically 3.9 µs per refresh command within a 32 ms or 64 ms total window) — regardless of actual cell leakage state, temperature, or system activity. The entire DRAM rank or selected banks are temporarily locked out of normal read/write access during each refresh event, introducing a deterministic but unavoidable latency penalty.

The core mechanism of static refresh was described in early Japanese patent literature from Matsushita (1993), which explained how a refresh demand signal is synchronized with CPU access cycles to arbitrate between read/write operations and refresh commands. The fundamental problem was identified in the same work: when refresh competes with active memory access, access latency increases and system throughput degrades — a constraint that becomes particularly acute in automotive real-time control loops where memory access latency must remain bounded.

IBM’s 2002 patent on cell leak monitoring directly frames the core argument: static refresh sets the refresh period conservatively to handle the worst measured leakage case. In automotive LPDDR5 applications, where the operating temperature ranges from −40°C to +125°C (AEC-Q100 Grade 2 or Grade 1), static refresh rates must be set for the worst-case high-temperature leakage condition. This produces excessive refresh activity during cold-start and normal operating temperatures — precisely when the vehicle’s power budget is most constrained.

Micron Technology’s 2008 patent on extended refresh periods demonstrated a first mitigation: reducing the cell plate voltage to half the supply voltage between refresh bursts during self-refresh mode, lowering discharge current from memory cell capacitors and enabling a reduced required refresh rate. While this technique reduces the power penalty of static self-refresh during automotive ECU standby states, it does not address the fundamental inflexibility of fixed-interval scheduling during active operation.

A further structural limitation in multi-bank DRAM architectures was identified by Intel Corporation in a 2018 patent: simultaneous self-refresh across all banks causes excessive peak current spikes, which is problematic in automotive power domains with strict supply rail noise budgets. Intel’s solution — staggering self-refreshes between banks — reduces instantaneous current demand without altering the fundamental static refresh interval, illustrating how static approaches require engineering workarounds to meet automotive electrical robustness requirements rather than solving the underlying scheduling problem.

Dynamic Refresh: Adaptive, Temperature-Aware, and Workload-Driven Strategies

Dynamic refresh departs from fixed-interval operation by modulating the refresh rate, scheduling, or granularity in response to real-time system state across six key adaptation axes: cell leakage monitoring, temperature compensation, workload-driven scheduling, per-bank and sub-array granularity, retention-aware targeting of weak cells, and ECC-assisted refresh period extension.

Leakage-Based Rate Adjustment

The most foundational dynamic approach is leakage-based refresh rate adjustment. IBM’s 2007 patent describes a monitor cell — designed to replicate the average or worst-case leakage behavior of actual array cells — used to measure real-time leakage. When leakage is severe at high temperature, the refresh cycle time is shortened by up to half. When leakage is undetectable at cold conditions, the refresh interval is doubled. This bidirectional adaptation directly addresses the automotive challenge of wide thermal cycling, where a fixed static rate would either over-refresh at low temperatures or under-refresh at thermal extremes.

“Static refresh sets the refresh period conservatively to handle the worst measured leakage case, which produces unnecessary refreshes and wasted power under typical conditions — dynamic refresh observes actual leakage and optimizes accordingly.”

Temperature-Compensated Self-Refresh

Temperature-compensated self-refresh is central to automotive LPDDR5 reliability. Mosaid Technologies’ 2009 patent describes a DRAM device that adjusts the self-refresh oscillator period using two chained frequency dividers: one compensating for process variation factors and the other for temperature-change factors. This two-dimensional compensation — addressing both process variation at advanced nodes (sub-10 nm) and temperature-driven leakage change — is essential because JEDEC standards for LPDDR5 mandate a 4x refresh rate increase above 85°C for low-power devices, making adaptive temperature response a specification requirement rather than a design choice.

Retention-Aware Per-Row Refresh

Retention-aware dynamic refresh extends adaptation to the granularity of individual rows. Freescale Semiconductor’s 2019 patent describes refreshing the bulk of DRAM rows at a slower, standard rate while identifying a subset of rows — those failing to meet data retention criteria at the standard rate — and refreshing them at a higher rate. This heterogeneous approach is significant because cell-to-cell variation increases with density scaling, and applying blanket worst-case refresh to every row when only a small fraction requires it is both power-inefficient and a source of unnecessary bus traffic in safety-critical systems. Academic research from Chung Yuan Christian University (2019) corroborates this approach, proposing an integrated scheme combining retention-aware auto-refresh with 2x granularity refresh to apply differentiated intervals based on weak-cell distribution profiles.

ECC-Integrated Self-Refresh Loops

ECC-integrated dynamic refresh represents a significant architectural advance for automotive LPDDR5 reliability. Qualcomm’s 2014 patent describes a DRAM array that, during self-refresh cycles, reads a portion of each row, performs error detection and correction, and selectively writes back corrected data — skipping write-backs when no errors are detected to save power. This combined self-refresh and self-correction loop is architecturally superior to static refresh in automotive contexts because it simultaneously maintains data integrity and reduces unnecessary write operations, directly addressing LPDDR5 reliability requirements under ISO 26262 functional safety standards. Samsung Electronics’ 2007 patent similarly uses ECC engine monitoring of tail-bit regions to dynamically control the self-refresh period in response to detected errors, enabling the refresh interval to actively respond to PVT (process, voltage, temperature) variation.

Security-Driven Randomised Refresh Addressing

ARM Limited’s 2017 patent introduces a further dimension of dynamic refresh: generating a randomised refresh address sequence — varying from cycle to cycle — to deter differential power analysis (DPA) attacks on secure data stored in DRAM. In automotive LPDDR5 systems handling cryptographic keys, secure boot data, or vehicle identity credentials, this dynamic randomised refresh strategy addresses security requirements that static sequential refresh cannot satisfy. This is particularly relevant for automotive systems running TEE-based (Trusted Execution Environment) workloads in line with AUTOSAR Adaptive Platform security architectures.

Automotive LPDDR5 Deployment: Where Refresh Strategy Becomes Safety-Critical

Automotive LPDDR5 deployment introduces requirements that amplify the importance of dynamic over static refresh in ways that differ fundamentally from mobile or server applications. A 2022 study by Mercedes-Benz confirmed that LPDDR5 delivers promised peak bandwidth gains of up to 50% over LPDDR4, but found that certain configurations provide no advantage over LPDDR4 for specific workloads — a finding that makes refresh strategy co-design with LPDDR5 configuration selection mandatory in automotive SoC designs.

Predictability of memory access latency is a particular concern in automotive real-time systems. Research from the University of Guelph and Intel (2018) demonstrated that DDR DRAM suffers from inherently variable access latencies due to factors including access patterns and memory state from previous accesses, making static refresh scheduling particularly problematic because it introduces unpredictable latency spikes when refresh preempts active row access. The paper advocates for memory architectures with predictable latency behavior — a recommendation directly applicable to automotive LPDDR5, which supports per-bank refresh (a form of dynamic refresh) to allow other banks to remain accessible during a refresh cycle.

Per-bank refresh is analyzed in depth in Intel Labs’ 2014 paper on parallelizing refreshes with accesses. The research shows that while LPDDR per-bank refresh alleviates some of the negative performance impact of rank-level static refresh, the round-robin scheduling constraint limits its effectiveness. The paper proposes non-sequential bank refresh scheduling to further exploit overlap between refresh and access operations. In automotive LPDDR5, where the standard explicitly supports per-bank refresh, controllers implementing dynamic bank-selection algorithms can significantly reduce worst-case access latency compared to static round-robin refresh — directly benefiting ADAS pipelines that share memory across CPU clusters, ISPs, and neural processing units.

Standby Power: PASR and Voltage-Reduced Self-Refresh

Partial array self-refresh (PASR), a dynamic technique applicable to automotive standby modes, is covered in Mosaid Technologies’ 2013 patent. PASR allows the memory controller to selectively refresh only the subblocks containing live data during vehicle sleep or ignition-off states, dramatically reducing standby power — a critical requirement for automotive systems that must maintain memory contents across key-off events with limited battery capacity. Static refresh, by contrast, refreshes the entire array unconditionally, drawing higher quiescent current from the vehicle battery during key-off events.

Voltage-reduced self-refresh (VRSR) is analyzed in research from IIT Ropar (2023). By reducing the supply voltage during self-refresh at normal and reduced temperature ranges, VRSR achieves meaningful energy savings while maintaining data integrity — a tradeoff that static self-refresh at nominal voltage cannot exploit. This is relevant to automotive LPDDR5 in scenarios where the vehicle is parked at low ambient temperatures and aggressive power management is required to meet quiescent current budgets mandated by automotive electrical system standards, as tracked by WIPO in its global patent database for automotive semiconductor innovations.

Head-to-Head: Static vs. Dynamic Refresh for Automotive LPDDR5

The fundamental trade-off between static and dynamic refresh for automotive LPDDR5 is between verifiability and efficiency. Static refresh provides a guaranteed, straightforward compliance path against JEDEC LPDDR5 tREF specifications and is easier to certify under ISO 26262 (ASIL B/D). Dynamic refresh maintains data integrity more precisely across the full automotive operating envelope but requires additional circuit complexity — leakage monitors, temperature sensors, ECC engines, and adaptive schedulers — each of which must itself be made functionally safe.

The Electronics and Telecommunications Research Institute (ETRI) patent from 2023 captures the most current state of the art: per-cell-set initial refresh period assignment with real-time adjustment based on collected information about each unit. This fully individualised dynamic refresh paradigm represents the logical endpoint of the evolution from static uniform refresh, and its alignment with LPDDR5’s enhanced per-bank and same-bank refresh (SBR) command set makes it the most architecturally compatible approach for next-generation automotive memory systems.

“Dynamic refresh can maintain data integrity more precisely across the full automotive operating envelope — but each adaptive component (leakage monitor, temperature sensor, ECC engine, adaptive scheduler) must itself be made functionally safe under ISO 26262.”

Patent Landscape: Who Is Shaping Automotive DRAM Refresh Innovation

Based on frequency and technical depth across a dataset of more than 45 patents and academic papers spanning from the early 1990s to 2025, seven organisations represent the dominant forces in DRAM refresh innovation relevant to automotive LPDDR5. The dataset covers memory technologies including DRAM, LPDDR3, LPDDR4, and LPDDR5, with major assignees including Micron Technology, Qualcomm, Intel, Huawei, Samsung Electronics, Freescale Semiconductor, ARM Limited, and Google.

Micron Technology

Micron is the most prolific patent assignee in static and hybrid refresh power reduction. Multiple patents describe cell plate voltage control and input buffer disabling during auto-refresh — techniques directly integrated into LPDDR5 low-power profiles. Micron’s approach to reducing cell plate voltage to half the supply voltage during inter-burst intervals represents the primary industry technique for reducing static self-refresh power consumption in automotive ECUs.

Qualcomm

Qualcomm has been particularly active in smart and autonomous refresh optimisation. Three 2016 patents establish Qualcomm as a leader in temperature-calibrated dynamic refresh for mobile and automotive SoCs, covering smart refresh, sub-array level autonomous refresh, and temperature-and-calibration-data-driven refresh scheduling. Qualcomm’s ECC-integrated self-correction loop (2014) is architecturally significant for automotive LPDDR5 reliability under ISO 26262.

ARM Limited

ARM contributes secure and deterministic refresh control, with patents from 2013 and 2017 establishing randomised address sequencing as a security-driven dynamic refresh technique relevant to automotive systems running TEE-based workloads. As the architect of the processor cores used in virtually all automotive SoCs, ARM’s refresh security patents have direct implementation relevance.

Freescale Semiconductor (NXP)

Freescale (now NXP) addresses automotive-specific per-row retention profiling, combining static baseline refresh with targeted high-rate refresh of weak rows — a hybrid strategy particularly suited to automotive MCU and SoC memory subsystems. NXP’s automotive focus makes this patent directly applicable to production vehicle platforms, as tracked in EPO filings for automotive semiconductor IP.

Google

Google represents the most recent innovation frontier with its 2025 traffic-aware adaptive precharge scheduler, demonstrating that dynamic refresh management continues to evolve at the memory controller level, with direct implications for the high-bandwidth, multi-tenant LPDDR5 memory subsystems used in automotive AI inference accelerators. Google’s 2025 patent computes priority scores for each DRAM bank group based on traffic parameters and selectively closes and precharges bank groups to create windows in which the refresh scheduler can operate with minimal latency impact.