Why EUV Lithography Needs DSA for Sub-30 nm Contact Holes

EUV lithography cannot reliably resolve contact holes at 3–5 nm technology nodes because single-exposure EUV is constrained by classical diffraction limits that prevent it from achieving the feature dimensions and pattern densities required at these nodes. Directed self-assembly (DSA) fills this gap by leveraging the molecular self-organisation of block copolymers (BCPs) to reduce contact hole dimensions below what top-down optical exposure can print alone. According to a Fudan University review published in 2020, DSA has been listed by the International Roadmap for Devices and Systems (IRDS) as a candidate lithography technique specifically for 3–5 nm technology node devices—explicitly alongside EUV and 193i immersion lithography as complementary advanced patterning techniques.

The core value proposition of EUV-DSA co-patterning is a top-down/bottom-up synergy. EUV prints a coarser guide pattern—a geometrically defined confining structure—within which the BCP spontaneously phase-separates into ordered nano-domains at dimensions that EUV cannot itself resolve. The resulting contact holes inherit the precision of molecular self-assembly rather than the resolution limit of the optical exposure tool. This combination, as identified by multiple patent assignees and academic reviewers in the dataset spanning 2013 to 2025, is described as essential for reaching the patterning requirements of advanced logic and memory device fabrication.

The dataset examined for this analysis encompasses patents and literature from 2013 to 2025, with assignees including Toshiba Corporation, Taiwan Semiconductor Manufacturing Co. (TSMC), GlobalFoundries, Fudan University, Universite de Bordeaux, IMEC VZW, and Zhangjiang National Laboratory. The dominant technical approaches within the DSA-relevant subset are graphoepitaxial self-assembly of BCPs, computational proximity correction methods tailored for DSA guide patterns, and integration of top-down lithographic prepatterns with bottom-up molecular self-assembly.

Block Copolymer Materials and Graphoepitaxial DSA Mechanisms for Contact Hole Shrink

The most extensively demonstrated BCP system for graphoepitaxial DSA contact hole patterning is poly(styrene-block-methyl methacrylate) (PS-b-PMMA), applied within geometrically defined prepattern openings created by top-down lithography. Toshiba Corporation’s 2013 study established the foundational process metrics for this approach: sub-30 nm contact holes were achieved using PS-b-PMMA within spin-on-carbon prepatterns developed via a wet development process. Within a prepattern hole critical dimension (CD) window of 70 ±5 nm, a 99.3% hole open yield was obtained, with a CD tolerance of 10 nm.

“Within a prepattern hole CD window of 70 ±5 nm, a 99.3% hole open yield was obtained with a CD tolerance of 10 nm—establishing the process window benchmark for graphoepitaxial DSA contact hole manufacturing feasibility.”

A critical process constraint identified by the Toshiba work is the matching between polymer domain size and prepattern geometry. Excessive mismatch between the BCP domain size and the prepattern hole CD causes a thick PS residual layer to remain at the hole bottom, preventing complete hole opening. This makes precise EUV CD control at the guide pattern level a direct prerequisite for DSA success—the two processes are tightly coupled, not independent.

The neutral layer underlying the BCP film plays a pivotal materials role in controlling self-assembly orientation. As disclosed by Universite de Bordeaux in a 2022 patent, a carbonaceous or fluorocarbonaceous neutral layer is deposited at a thickness greater than 1.5 times the BCP film thickness, cross-linked, and then coated with a silylated BCP. This architecture enables perpendicular orientation of BCP nano-domains—a geometry essential for forming through-hole contact structures. Selective removal of one nano-domain (e.g., PMMA) then creates the lithographic mask pattern for etch transfer into the substrate.

DSA achieves resolution enhancement by circumventing the classical diffraction limit of optical exposure through molecular assembly mechanisms. The Fudan University 2020 review articulates this as a top-down/bottom-up synergy in which combinations of DSA with EUV and 193i immersion lithography further enhance patterning resolution and device density beyond what either approach achieves independently. BCP self-assembly has been broadly applied in the fabrication of non-volatile memories, FinFETs, and photonic nanodevices—device families that all require dense, precisely positioned contact holes.

Process Integration: EUV Guide Patterns, DSA-OPC, and Pattern Density Multiplication

Integrating EUV lithography with DSA requires careful co-optimisation of the EUV-printed guide pattern and the BCP self-assembly behaviour—because the relationship between guide pattern geometry and DSA output is non-linear and thermodynamically governed, not a simple one-to-one mapping. GlobalFoundries addressed this computationally in 2014 through a DSA process/proximity correction methodology using self-consistent field (SCF) theory to linearise the DSA response to guide pattern modifications. The method implements an iterative correction loop: a DSA model is applied to the target pattern, a residual is computed, and the guide pattern is updated until convergence. This DSA-aware optical proximity correction (OPC) directly solves the translation problem between what EUV prints and what the BCP needs as a confining geometry.

TSMC has pursued a related design automation approach at the circuit level. A 2019 TSMC patent describes a method in which a DSA process derives a guide pattern from a first target pattern containing two sets of target features. Sub-DSA-resolution assistant features (SDAFs) are inserted into a second target pattern to connect guide features, controlling how the BCP interprets boundary conditions between adjacent holes. This enables a single EUV exposure to produce a guide pattern from which DSA generates multiple contact holes with the correct pitch and CD—achieving density multiplication that EUV alone cannot deliver at equivalent cost.

The density multiplication imperative is also formalised in a 2024 patent from Zhangjiang National Laboratory, which explicitly identifies the “top-down” optical lithographic approach and the “bottom-up” BCP-DSA technique as complementary patterning methodologies and proposes their organic integration to achieve further reduction in pattern dimensions and further increase in pattern density. The patent highlights that BCP self-assembly has been broadly applied in the fabrication of non-volatile memories, FinFETs, and photonic nanodevices. According to standards bodies such as IEEE and roadmapping organisations like the Semiconductor Industry Association, pattern density and feature scaling remain the primary drivers of advanced node process development.

Key Players and Innovation Trends in EUV-DSA Co-Patterning

The EUV-DSA innovation landscape traces a clear arc from materials science through process engineering to design automation—the full stack required for volume manufacturing. Analysis of the dataset reveals five organisations at distinct layers of this stack, each contributing an essential component of the EUV-DSA contact hole patterning capability.

Toshiba Corporation — Foundational Process Metrics

Toshiba contributed the earliest systematic evaluation of DSA readiness for semiconductor manufacturing. The 2013 study established quantitative process window metrics—99.3% hole open yield and 10 nm CD tolerance—that remain the benchmark for feasibility assessment of graphoepitaxial DSA contact hole processes. The work also identified the polymer-prepattern size matching constraint as the primary process-limiting variable.

GlobalFoundries — Computational DSA-OPC Framework

GlobalFoundries’ 2014 DSA-OPC patent provided the EDA-level toolchain necessary for designing EUV guide patterns that yield accurate DSA outcomes for contact holes. By applying SCF theory to linearise the DSA response and implementing an iterative correction loop, GlobalFoundries addressed the fundamental challenge that the BCP self-assembly process is non-linear and cannot be corrected using conventional lithographic OPC methods. According to WIPO patent data, this computational approach represents a distinct IP cluster within the broader EUV patterning landscape.

TSMC — Circuit-Level DSA Design Automation

TSMC is the most prolific assignee in the broader EUV dataset. The 2019 DSA patent addresses the circuit-level design rule challenge: how to derive a manufacturable EUV guide pattern from a circuit-level target pattern containing multiple contact hole features at sub-DSA-resolution spacings. The SDAF methodology enables density multiplication from a single EUV exposure, directly reducing the number of mask layers and exposure steps required at advanced nodes.

Universite de Bordeaux — Neutral Layer Materials IP

Universite de Bordeaux (Grenoble Alpes University) has made IP-protected advances in neutral layer engineering that are a prerequisite for using DSA as a contact hole lithography mask. Their 2022 dual filings in Singapore and China indicate an international commercialisation strategy targeting Asia-Pacific foundry markets where advanced node manufacturing is concentrated. The perpendicular BCP orientation enabled by their neutral layer architecture is not achievable with conventional underlayer chemistries.

Fudan University and Zhangjiang National Laboratory — China’s Growing DSA IP Presence

Fudan University’s 2020 review and Zhangjiang National Laboratory’s 2024 patent reflect both the maturing academic understanding of DSA physics in China and a growing institutional IP interest in BCP-based patterning for next-generation nodes. The Zhangjiang patent explicitly formalises the EUV-DSA integration as a density multiplication and dimension shrink platform targeting advanced memory and logic device fabrication—aligning Chinese institutional research with the IRDS roadmap priorities identified in the Fudan review. Research institutions tracked by OECD innovation metrics increasingly cite China’s semiconductor IP output as a significant and growing component of global advanced patterning research.

“The innovation arc from Toshiba’s 2013 process characterisation through GlobalFoundries’ 2014 EDA framework to TSMC’s 2019 circuit-level design automation traces the full stack required for EUV-DSA contact hole patterning in volume manufacturing.”

An important trend across the dataset is the shift from proof-of-concept DSA demonstrations toward manufacturing-readiness metrics. Toshiba quantified hole open yield and prepattern CD tolerance; GlobalFoundries addressed the EDA challenge of guide pattern synthesis; TSMC addressed the circuit-level design rule challenge; and Fudan and Zhangjiang addressed the density multiplication imperative driven by the IRDS roadmap. The IMEC VZW is also listed among the dataset assignees, reflecting the role of European research consortia in advancing DSA process integration alongside foundry and academic partners.