Block Copolymer Materials and Graphoepitaxial DSA Mechanisms for Contact Hole Shrink

Directed self-assembly enables sub-30 nm contact holes by leveraging the molecular self-organization of block copolymers (BCPs) within lithographically defined prepattern openings — producing feature dimensions that EUV or 193i immersion lithography cannot reliably print alone. The most extensively demonstrated BCP system for this application is poly(styrene-block-methyl methacrylate) (PS-b-PMMA), applied within graphoepitaxially defined prepatterns. According to WIPO, advanced patterning techniques including DSA are critical enablers for continued semiconductor scaling under the current international IP landscape.

Toshiba Corporation’s 2013 study on graphoepitaxial DSA lithography established the quantitative process window for this approach: within a prepattern hole critical dimension (CD) window of 70 ± 5 nm, a 99.3% hole open yield was achieved, with a CD tolerance of 10 nm. The study also identified a critical process constraint — mismatch between BCP domain size and prepattern hole CD causes a thick PS residual layer at the hole bottom that prevents complete opening. This makes precise EUV CD control at the guide pattern level a prerequisite for DSA success, not merely a convenience.

DSA achieves resolution enhancement by circumventing the classical diffraction limit of optical exposure through molecular assembly mechanisms. The neutral layer underlying the BCP film plays a pivotal materials role in controlling self-assembly orientation. As disclosed in a 2022 patent from Universite de Bordeaux, a carbonaceous or fluorocarbonaceous neutral layer is deposited at a thickness greater than 1.5 times the BCP film thickness, cross-linked, and then coated with a silylated BCP. This architecture enables perpendicular orientation of BCP nano-domains, which is essential for forming through-hole contact structures. Selective removal of one nano-domain — for example, PMMA — then creates the lithographic mask pattern for etch transfer into the substrate.

The Universite de Bordeaux’s dual patent filings in Singapore and China in 2022 confirm a global commercialization strategy for this neutral layer architecture — signalling that neutral layer engineering has transitioned from academic concept to protectable IP in the EUV-DSA integration stack.

Process Integration: EUV Guide Patterns, Computational DSA Proximity Correction, and the OPC Challenge

Integrating EUV lithography with DSA requires co-optimization of the EUV-printed guide pattern and the BCP self-assembly behavior — a challenge that is not trivially solved due to the non-linear, thermodynamically governed nature of BCP phase separation. GlobalFoundries addressed this computationally in a 2014 patent disclosing a DSA process/proximity correction methodology that uses self-consistent field (SCF) theory to linearize the DSA response to guide pattern modifications. An iterative correction loop applies a DSA model to the target pattern, computes a residual, and updates the guide pattern until convergence — directly addressing the translation problem between what EUV prints and what DSA needs as a confining geometry.

“DSA-aware OPC directly addresses the translation problem between what EUV prints and what DSA ultimately needs as a confining geometry — without it, guide pattern design for contact holes is a trial-and-error process.”

TSMC pursued a related design automation approach at the circuit level, disclosed in a 2019 patent on integrated circuit manufacturing with DSA. In this method, a DSA process derives a guide pattern from a first target pattern containing two sets of target features. Sub-DSA-resolution assistant features (SDAFs) are inserted into the second target pattern to connect guide features, controlling how the BCP interprets boundary conditions between adjacent holes. This enables a single EUV exposure to produce a guide pattern from which DSA generates multiple contact holes with the correct pitch and CD — achieving density multiplication that EUV alone cannot deliver at equivalent cost. Standards bodies including IEEE have highlighted such design-process co-optimization as a defining challenge for sub-5 nm node manufacturing.

Density Multiplication and the IRDS Roadmap Imperative for 3–5 nm Nodes

The International Roadmap for Devices and Systems (IRDS) explicitly lists DSA alongside EUV as a candidate lithography technique for 3–5 nm technology node devices, recognising that single-exposure EUV is insufficient for the contact hole density required at these nodes. A 2020 review from Fudan University articulates this directly: DSA combined with EUV and 193i immersion lithography further enhances patterning resolution and device density beyond what either approach achieves independently — the top-down/bottom-up synergy being central to the technology’s value proposition for contact hole layers.

Zhangjiang National Laboratory’s 2024 patent on patterning methods for semiconductor processes formalizes the EUV-DSA integration framework, explicitly identifying top-down optical lithographic approaches and bottom-up BCP-DSA techniques as complementary patterning methodologies. The patent proposes their organic integration to achieve further reduction in pattern dimensions and increase in pattern density, and highlights that BCP self-assembly has been broadly applied in the fabrication of non-volatile memories, FinFETs, and photonic nanodevices — device families that all require dense, precisely positioned contact holes. Research published by institutions tracked by Nature has similarly confirmed that BCP self-assembly at the sub-10 nm scale is a materials science frontier with direct semiconductor manufacturing relevance.

Key Players, Innovation Arc, and What the IP Landscape Signals for Advanced Patterning

The EUV-DSA co-patterning IP landscape traces a clear innovation arc from material science through process engineering to design automation — the full stack required for contact hole patterning in volume manufacturing. Analysis of the dataset, which spans patents and literature from 2013 to 2025 and includes assignees from Toshiba, TSMC, GlobalFoundries, Fudan University, Universite de Bordeaux, IMEC VZW, and Zhangjiang National Laboratory, reveals five distinct organisations at the forefront of this integration.

Toshiba Corporation — Foundational Process Characterisation

Toshiba’s 2013 study established quantitative process window metrics — 99.3% hole open yield and 10 nm CD tolerance — that remain the benchmark for DSA feasibility assessment in contact hole applications. The work was among the earliest systematic evaluations of DSA lithography readiness for semiconductor manufacturing.

TSMC — Circuit-Level Design Rule Integration

TSMC is the most prolific assignee in the broader EUV dataset and has explicitly filed on DSA integration for IC manufacturing. The 2019 patent on DSA guide pattern derivation and sub-resolution assistant features represents a direct EUV-DSA co-design strategy at the circuit level. TSMC’s broader EUV portfolio, including EUV double patterning work developed in collaboration with IBM, contextualises DSA as one of multiple resolution enhancement strategies operating in concert with EUV. The PatSnap Insights blog has tracked TSMC’s EUV-related IP activity across multiple technology generations.

GlobalFoundries — EDA-Level Guide Pattern Synthesis

GlobalFoundries’ 2014 DSA-OPC framework provides the EDA-level toolchain necessary for designing EUV guide patterns that yield accurate DSA outcomes for contact holes. Without this computational layer, translating a target contact hole layout into a manufacturable EUV guide pattern remains intractable for complex circuit geometries.

Universite de Bordeaux / Grenoble Alpes University — Neutral Layer IP

The dual filings in Singapore and China in 2022 for the carbonaceous/fluorocarbonaceous neutral layer architecture indicate an active international commercialization strategy for this critical materials enabler. Perpendicular BCP nano-domain orientation — required for through-hole contact structures — depends on this neutral layer design. According to the European Patent Office, cross-border filing strategies of this type are characteristic of technologies approaching commercial deployment readiness.

Fudan University and Zhangjiang National Laboratory — China’s Growing DSA IP Presence

Fudan’s 2020 review of DSA for sub-10 nm fabrication and Zhangjiang’s 2024 patterning patent reflect both a maturing academic understanding of DSA physics and a growing industrial IP interest in BCP-based patterning for next-generation nodes. Together, they signal that China’s semiconductor research institutions are actively building IP positions in the EUV-DSA integration space, targeting advanced memory and logic device fabrication. The PatSnap innovation intelligence platform provides detailed assignee-level analysis for tracking this emerging competitive landscape.

“The innovation arc in EUV-DSA co-patterning runs from material science through process engineering to design automation — the full stack required for contact hole patterning in volume manufacturing at 3–5 nm nodes.”

An important trend across the dataset is the shift from proof-of-concept DSA demonstrations toward manufacturing-readiness metrics. Toshiba quantified hole open yield and prepattern CD tolerance; GlobalFoundries addressed the EDA challenge of guide pattern synthesis; TSMC addressed circuit-level design rule integration; and Fudan and Zhangjiang addressed the density multiplication imperative driven by the IRDS roadmap. This progression confirms that EUV-DSA contact hole patterning is no longer a research curiosity — it is an active IP battleground for the next generation of logic and memory devices.