FinFET Architecture and Its Leakage Current Mechanisms

The FinFET was developed explicitly to address the escalating leakage currents that plagued planar MOSFETs as channel lengths shrank below 20 nm. Its tri-gate structure — where the gate wraps around three sides of a thin silicon fin — delivers better electrostatic control of the channel than a planar gate. However, bulk FinFETs still suffer from a punch-through leakage path running beneath the fin through the region adjacent to shallow trench isolation (STI), a region the gate does not fully control. This punch-through component is temperature-dependent: it becomes more significant at intermediate temperatures but is suppressed when carrier thermal energy is reduced at cryogenic conditions, according to TSMC’s foundational FinFET patent documentation.

At cryogenic temperatures, subthreshold leakage in FinFETs is governed primarily by the exponential dependence on thermal voltage kT/q. Since subthreshold current follows an Arrhenius-like dependence — I_sub ∝ exp(–qV_th/nkT) — cooling to 77 K or 4 K dramatically suppresses the thermionic emission component. However, the FinFET’s partially depleted fin body, particularly in bulk FinFET configurations, can accumulate charge (the floating body effect). IBM’s documentation of SOI FinFET stability identifies this as producing history-dependent threshold voltage shifts and anomalous leakage current spikes known as “kink” effects — effects that become more pronounced at low temperatures due to freeze-out of minority carriers.

Work function engineering in drain gate regions — as explicitly addressed by Kyungpook National University’s high-density FinFET patent — targets the non-uniform potential distribution across the fin body that creates localised leakage paths. At cryogenic temperatures, reduced carrier scattering can enhance channel mobility but simultaneously sharpens the threshold voltage roll-off, amplifying the sensitivity of leakage current to gate-voltage deviations. For circuits operating at 4 K where voltage margins are narrow, this is a significant design concern. Self-heating effects in FinFETs — documented by South China University of Technology — are reduced at cryogenic temperatures, but the fin’s limited heat dissipation capacity means thermal gradients can still emerge during pulsed operation, directly coupling channel temperature to leakage current variation.

Nanosheet FET Architecture and Leakage Current Characteristics

The nanosheet (gate-all-around, GAA) transistor provides circumferential gate control over each individual sheet — a geometry fundamentally superior to FinFET’s three-sided tri-gate. This superior electrostatic integrity directly translates to lower minimum subthreshold swing (SS) and lower drain-induced barrier lowering (DIBL) than comparable FinFETs. However, Chungbuk National University’s 2025 nanosheet patent explicitly frames the architecture as a successor to FinFET that still faces a critical limitation: “the inability to control the leakage current existing in the substrate.” To address this, a Silicon-On-Nothing (SON) technique creates a defect layer inside the substrate that improves OFF-state leakage current while simultaneously increasing ON-state drive current — a dual benefit especially relevant in cryogenic applications.

Leakage variability in multi-stack nanosheet devices is further complicated by parasitic bottom transistors. POSTECH’s 2020 analysis of source/drain recess depth variations in silicon nanosheet FETs quantifies how excessive recess depth causes dopants to diffuse into a parasitic bottom transistor region below the nanosheet stack, increasing off-state current (I_off) in ways that cannot be gated off. At cryogenic temperatures, dopant freeze-out reduces the active carrier concentration in these parasitic regions, which can partially mitigate this parasitic I_off component — an effect not present in FinFETs where the parasitic leakage path through the fin base behaves differently. This asymmetry in freeze-out behavior represents a key differentiator between the two architectures at cryogenic temperatures, as documented by researchers at POSTECH.

Samsung Electronics has characterised band-to-band tunneling (BTBT) leakage specifically in the context of co-integrated Si and non-Si nanosheet FETs. In Samsung’s patent on low-BTBT co-integrated nanosheet FETs, the leakage current ratio between non-Si and Si nanosheet FETs is explicitly measured, with non-Si (e.g., InGaAs) nanosheets exhibiting higher BTBT leakage due to their narrower bandgap. At cryogenic temperatures, BTBT leakage does not follow the same Arrhenius suppression as thermionic leakage — it is dominated by quantum mechanical tunneling probability, which is far less sensitive to temperature reduction. This means that at cryogenic temperatures, BTBT-dominated nanosheet leakage may represent a larger fraction of total off-current than at room temperature, a more severe problem for narrow-gap nanosheet materials than for conventional silicon FinFETs.

“At cryogenic temperatures, BTBT-dominated nanosheet leakage may represent a larger fraction of total off-current than at room temperature — a more severe problem for narrow-bandgap nanosheet materials than for conventional silicon FinFETs.”

Xidian University’s 2024 stacked nanosheet patent acknowledges that although nanosheet FETs “optimize short-channel effects and achieve stronger gate control,” a residual leakage current persists because at shorter gate lengths “gate control is not perfect.” The proposed solution — recessed channel structures that redistribute fringing electric fields at the channel–extension junction boundary — reduces peak edge electric fields and thereby suppresses leakage. At cryogenic conditions, these fringing-field-driven leakage components are additionally suppressed by reduced carrier thermal energy, but the geometric advantage of the nanosheet architecture amplifies that benefit relative to FinFETs.

Physical Mechanisms Differentiating Cryogenic Leakage in Both Architectures

Several fundamental physical mechanisms distinguish the leakage behavior of FinFETs versus nanosheet FETs at cryogenic temperatures. The first is the subthreshold carrier transport regime. IBM’s low-leakage CMOS logic patent establishes that subthreshold leakage arises because current flows from drain to source when gate and source voltages are equal, driven by the potential barrier height for majority carriers, with the dependence I_sub ∝ exp(–qV_th/nkT). Cooling to 4 K reduces kT by approximately 75×, theoretically suppressing subthreshold leakage by orders of magnitude in both FinFETs and nanosheets — but the nanosheet architecture, with its lower subthreshold slope (ideality factor n closer to 1 due to the full surrounding gate), achieves a steeper temperature-dependent suppression. Standards bodies including IEEE have documented the fundamental relationship between gate electrostatic integrity and subthreshold slope in advanced transistor nodes.

Gate dielectric tunneling represents a second leakage pathway. IBM’s 2009 integrated circuit leakage reduction patent documents that gate dielectric tunneling current (I_TUN) flows between gate and channel when they are at different potentials and is relatively temperature-independent. Both FinFETs and nanosheets employ high-k dielectrics, but nanosheet FETs with their wrapped gate structure have a larger effective gate-to-channel interface area per transistor footprint, potentially resulting in higher absolute tunneling leakage per unit area at cryogenic temperatures where this mechanism is not thermally suppressed. Research published through institutions such as Nature has highlighted tunneling as a persistent challenge in scaled high-k gate stacks.

A critical concern unique to cryogenic operation is carrier freeze-out in the bulk substrate. TSMC’s FinFET documentation notes that SOI FinFETs benefit from the buried oxide blocking substrate leakage currents. At 4 K, the non-uniform charge distributions from dopant freeze-out can generate anomalous leakage paths at fin–STI or nanosheet–substrate interfaces. Zhejiang University’s 2024 multiphysics subthreshold simulation framework explicitly couples quantum transport, heat conduction, and elastic mechanics for nanoscale devices including FinFETs, demonstrating that thermal-stress-induced band structure modification alters subthreshold conduction characteristics — effects that intensify at extreme temperatures. Nanosheet FETs, being more fully depleted due to their thin body geometry, are less susceptible to freeze-out-induced leakage inhomogeneity than partially depleted FinFETs.

Contact resistance at stacked nanosheet source/drain interfaces is a further differentiator. POSTECH’s 2018 study on SOI FinFETs with different silicide thickness demonstrates that parasitic resistance associated with silicide contact layers directly affects subthreshold characteristics and threshold voltage — both temperature-sensitive parameters. In nanosheet FETs, contact resistance at the ends of multiple stacked sheets is a significant concern. Applied Materials’ 2024 patent on nanosheet contact resistance reduction addresses selective silicidation processes that control nanosheet channel length at source/drain ends and perform metal fill across all stack layers. At cryogenic temperatures, contact resistance typically increases as reduced carrier density offsets phonon scattering reduction, which can suppress on-current more severely in nanosheet devices with their multiple contact interfaces — indirectly raising the apparent I_off/I_on ratio concern at 4 K. The WIPO patent landscape reflects sustained industry investment in contact resistance reduction across both architectures.

Head-to-Head: FinFET vs. Nanosheet Leakage at Cryogenic Temperatures

The fundamental architectural difference — FinFET’s three-sided gate control versus nanosheet’s circumferential gate-all-around control — translates directly into electrostatic leakage suppression advantage at all temperatures, including cryogenic. Qualcomm’s FinFET CMOS circuit patent explicitly acknowledges that FinFETs can suffer from increased leakage, reduced threshold voltage, and threshold voltage roll-off under short-channel effects, requiring diffusion interrupt isolation structures to mitigate inter-device leakage coupling. Nanosheet FETs, by virtue of full channel encapsulation, exhibit intrinsically lower DIBL and better subthreshold swing — meaning at cryogenic temperatures their subthreshold characteristic is both steeper and more ideal, with leakage suppressed more effectively as temperature decreases.

However, nanosheet FETs introduce unique cryogenic challenges absent in FinFETs. The substrate leakage path identified in Chungbuk National University’s 2025 nanosheet patent — current leaking through the silicon substrate beneath the stacked sheets — does not have a direct FinFET analog where STI and fin geometry limit such paths. The SON substrate isolation technique proposed in that patent directly improves OFF-state current by blocking this substrate path, a more architecturally complex solution than the STI-based isolation used in FinFETs. At cryogenic temperatures, substrate leakage suppression through freeze-out aids both architectures, but the multi-layer stacking of nanosheets creates more interface area for trap-assisted tunneling — a mechanism that is only weakly temperature-dependent and therefore becomes proportionally more important at 4 K.

Threshold voltage (V_th) behavior at cryogenic temperatures diverges between the two architectures in a critical way. In FinFETs, V_th increases significantly with cooling due to dopant freeze-out and reduced subthreshold slope, but the floating body effect — especially in SOI FinFETs, as documented in IBM’s integrated circuit array stability patent — can produce threshold voltage instability where accumulated charge shifts V_th unpredictably. Nanosheet FETs, being fully depleted by design, are less susceptible to floating body instability, leading to more predictable V_th increase at cryogenic temperatures and correspondingly more stable (though still reduced) off-state leakage current.

Samsung’s hot electron over-excitation tunnel FET patent implements nanosheet stacks that combine tunnel FET and thermionic FET channels. This is directly relevant to cryogenic leakage because TFET-style operation relies on band-to-band tunneling rather than thermionic emission. At cryogenic temperatures, thermionic leakage collapses while tunneling leakage persists, meaning that combined TFET/hot-electron nanosheet structures may exhibit a leakage floor dominated by quantum tunneling that does not scale with temperature — a fundamental differentiator from conventional FinFETs whose leakage is more completely thermally suppressed at cryogenic conditions. The implications for quantum computing interface electronics — where transistors must operate reliably at millikelvin to 4 K temperatures — are tracked extensively in the PatSnap innovation intelligence platform.

The patent corpus reviewed — spanning assignees including Samsung Electronics, POSTECH, Kyungpook National University, Chungbuk National University, Xidian University, South China University of Technology, TSMC, Qualcomm, IBM, and Applied Materials — reflects a consistent industry trajectory: nanosheet FETs are the preferred architecture for advanced nodes requiring minimal leakage, but the cryogenic operating environment introduces a distinct set of challenges that are not simply extensions of room-temperature behavior. For quantum computing interface electronics, cryogenic memory, and low-power semiconductor design operating at 4 K, the choice between FinFET and nanosheet architectures involves trade-offs between established FinFET punch-through and floating body risks versus nanosheet-specific substrate leakage, BTBT floors, and contact resistance challenges. The PatSnap R&D intelligence platform provides full access to this evolving patent landscape.