Why the Industry is Moving Beyond FinFET
The semiconductor industry is transitioning from FinFET to Gate-All-Around (GAA) transistor architectures because FinFET technology has reached fundamental physical limits in meeting the scaling requirements of active devices at 3nm nodes and below. GAA transistors — spanning Multi-Bridge-Channel FET (MBCFET), nanosheet, and forksheet configurations — have emerged as the leading FinFET replacements due to their superior electrostatic controllability and improved suppression of short-channel effects.
The evolution from planar MOSFETs to FinFETs and then to GAA architectures reflects a continuous industry pursuit of higher device density and enhanced performance. GAA nanosheet FETs provide superior gate control by surrounding the gate around all four sides of the channel, producing higher “ON” current and improved electrostatic control compared to FinFETs. The technology delivers a 65 mV/dec sub-threshold swing at short gate lengths, higher DC performance at reference footprint, and design flexibility through variable nanosheet widths.
Three primary technical objectives drive GAA development: co-optimising performance and power through simultaneous channel release of nanosheets with multi-width capabilities; managing the crystallographic plane transition from (110) to (100) orientation, which increases electron mobility but decreases hole mobility; and enabling ultra-high integration with low power consumption suited to AI and data-centric computing workloads. According to WIPO, transistor architecture patents have been among the fastest-growing categories in global semiconductor IP filings as the industry approaches these physical limits.
GAA nanosheet transistors achieve a 65 mV/dec sub-threshold swing at short gate lengths, with gate structures surrounding all four sides of the channel to deliver higher ON current and improved electrostatic control compared to FinFET devices.
A GAA transistor is an advanced device architecture in which the gate electrode wraps around the channel on all four sides. This geometry provides tighter electrostatic control than FinFET, reduces leakage current, and suppresses short-channel effects — making it the preferred architecture for semiconductor nodes at 3nm and below.
A USD 5.93 Billion Market Taking Shape
The GAA Field Effect Transistor market is growing from USD 3.61 billion in 2025 to USD 3.83 billion in 2026, with a projected CAGR of 7.33% carrying it to USD 5.93 billion by 2032. This trajectory is driven by the escalating performance-per-watt requirements of AI training and inference, high-performance computing, premium mobile devices, and software-defined vehicles.
Market adoption is being accelerated by the tunability advantages of nanosheet-based GAA devices. Wider nanosheets deliver enhanced drive current for high-performance applications, while narrower nanosheets occupy smaller footprints for power-efficient designs. This architectural flexibility makes GAA technology attractive across multiple application domains simultaneously.
However, the transition also reshapes the entire semiconductor value chain. Advanced patterning requirements, gate stack integration complexities, and variability control demands are creating new market opportunities for specialised equipment and materials suppliers. Geopolitical factors add further complexity: supply chain resilience spanning materials, tools, wafers, and packaging has become as strategically important as device physics performance, according to analysts tracking semiconductor policy at OECD.
The GAA Field Effect Transistor market is projected to grow from USD 3.61 billion in 2025 to USD 3.83 billion in 2026, reaching USD 5.93 billion by 2032 at a compound annual growth rate of 7.33%.
MBCFET, Nanosheet, and Forksheet: Architecture Trade-offs
The three leading GAA variants each address different engineering priorities, and choosing among them requires understanding their distinct structural approaches, performance characteristics, and manufacturing complexity profiles. MBCFET offers the lowest migration cost; nanosheet provides the broadest design flexibility; forksheet targets the most aggressive area scaling.
MBCFET: The Pragmatic Migration Path
Multi-Bridge-Channel FET technology utilises 90% or more of existing FinFET manufacturing processes, requiring only a few revised masks for migration. This compatibility significantly reduces capital expenditure and accelerates time-to-market. MBCFET achieves 65 mV/dec sub-threshold swing at short gate lengths and provides higher effective channel width at a reference footprint, with design flexibility through variable nanosheet widths that can satisfy different requirements in a single chip with minimal areal cost.
Nanosheet: The Design-Flexible Workhorse
Nanosheet transistors use multiple horizontally stacked channel layers with thickness ranging from 3 to 8 nanometers, with gate structures surrounding all surfaces of each sheet. The architecture enables simultaneous channel release of nanosheets with multi-width capabilities, allowing co-optimisation of performance and power. Samsung Electronics and TSMC have advanced nanosheet development furthest toward pilot production among commercial foundries, with TSMC targeting 2nm GAA production for 2025.
Forksheet: The Area-Scaling Frontier
Forksheet configurations integrate NMOS and PMOS nanosheet structures on either side of a dielectric wall, addressing the need for smaller spacing between NMOS and PMOS devices in standard cells. This offers better scalability of area and performance but introduces additional complexity: T-shaped backbone structures, dielectric wall integration, and sophisticated metal gate interconnect solutions. IBM’s forksheet technology features complementary CMOS devices with tunable effective width ratios (β), enabling precise transistor spacing and β tuning. A pending IBM patent (US20250151373A1, filed November 2023) specifically addresses the challenge of patterning lithography masks for forksheet FETs using a T-shaped backbone with dielectric sub-walls.
“MBCFET utilises 90% or more of FinFET processes with only a few revised masks — allowing easy migration from FinFET process while delivering superior gate control and higher ON current.”
Explore the full GAA patent landscape — MBCFET, nanosheet, and forksheet filings mapped by assignee and technology cluster.
Search GAA Patents in PatSnap Eureka →The Process Integration Challenges Holding GAA Back
GAA transistor fabrication faces several critical process integration challenges that directly affect both yield and cost at scale. Channel release, gate dielectric uniformity, mechanical stability, and crystallographic orientation management are the four most consequential hurdles across all GAA variants.
Channel Release and Etch Selectivity
The selective removal of sacrificial SiGe layers to release and suspend silicon nanosheet channels requires high etching selectivity of SiGe over Si. This is particularly critical for multi-width nanosheet co-optimisation, where simultaneous channel release across sheets of different widths must be achieved without dimensional loss. Precise control of etch rates, uniformity, and endpoint detection is essential to create uniform gaps for gate material deposition while maintaining the mechanical stability of suspended nanostructures.
GAA nanosheet fabrication requires extra gate oxide layers of 4.0–5.0 nm thickness for reliable operation at voltages above 1.0V, and nanosheet mechanical stability becomes problematic under compressive stress from source/drain regions for channel lengths exceeding 100 nm.
Gate Dielectric Uniformity in Confined Spaces
Achieving uniform gate dielectric thickness in the confined vertical spacing between stacked nanosheet channels is a manufacturing precision challenge with direct reliability implications. Extra gate oxide layers require 4.0–5.0 nm thickness for reliable operation at voltages above 1.0V. Conformal deposition techniques must ensure uniform coverage on all surfaces of the three-dimensional channel geometry — a requirement that becomes more demanding as inter-sheet spacing shrinks with further scaling.
Crystallographic Orientation and Mobility Engineering
The transition from FinFET’s (110) crystallographic plane to GAA’s (100) orientation increases electron mobility but decreases hole mobility, requiring compressive stress engineering for N/P current matching. Strain engineering methods — including strained silicon-germanium layers, stress-inducing capping layers, and lattice-mismatched epitaxial growth — must be carefully balanced against thermal budget constraints and structural stability requirements throughout the fabrication sequence. Research published through institutions tracked by IEEE has highlighted this mobility trade-off as one of the most active areas of GAA process research.
Forksheet-Specific Complexity
Forksheet technology introduces additional integration challenges through its T-shaped backbone structures and dielectric wall requirements for NMOS/PMOS separation. Three-dimensional stacking implementations face work-function metal layer differentiation challenges between upper and lower transistor levels, necessitating advanced replacement metal gate (RMG) inner spacer protection mechanisms. A pending IMEC patent (US20260013203A1, filed September 2022) addresses work function mismatch between inner and outer gates in GAA structures, proposing a thickness ratio of 4:1 or higher and a work function difference of ±250 meV to simplify fabrication while maintaining device performance.
Commercial viability of optimised GAA manufacturing processes has been demonstrated through fully functional high-density SRAM circuits, providing confidence for large-scale deployment across advanced technology nodes while validating that the process integration challenges described above are solvable at wafer scale.
Who Leads the GAA Race: Samsung, TSMC, IBM, and Beyond
The competitive landscape for GAA transistor development is bifurcated: established foundries — Samsung Electronics and TSMC — are accelerating commercial nanosheet deployment, while research-focused organisations including IBM and IMEC are pioneering the more complex MBCFET and forksheet architectures. Intel, GlobalFoundries, and Chinese players including SMIC face more substantial process integration challenges in scaling GAA manufacturing.
Samsung Electronics
Samsung has developed comprehensive GAA transistor technology with a focus on nanosheet architectures. Their approach includes multi-layer nanosheet stacking with sacrificial layer removal techniques for gate formation, innovative channel region designs with variable width active segments, and symmetric nanosheet structures for optimised performance. Samsung’s technology features multi-stacked transistor configurations combining nanosheet transistors in zebra-like arrangements, SOI substrates with SiGe/Si unit bilayers, and forksheet transistor structures with early-formed gate cut architectures. The company also applies stress engineering methods and controlled inter-sheet spacing for enhanced device performance.
TSMC
TSMC’s GAA development concentrates on memory applications and multi-device integration. Their GAA SRAM implementations feature transistors with different threshold voltages and work functions within the same cell sizes. The company has developed integrated solutions combining GAA devices with stacked FinFET structures — using GAA transistors in low-power circuits and stacked FinFET devices in I/O circuits. TSMC’s technology also features sophisticated back-side contact structures for GAA nanosheet transistors, including VDD/VSS power delivery through back-side metallisation. TSMC is targeting 2nm GAA production for 2025.
IBM
IBM has developed advanced GAA technologies with particular expertise in forksheet architectures and hybrid integration. Their forksheet technology features complementary CMOS devices with tunable effective width ratios (β) for precise transistor spacing and β tuning. IBM has also pioneered tapered channel forksheet transistors with improved electrostatic control, and developed co-integration of GAA nanosheets and comb-like nanosheet devices on the same substrate — enabling power-performance-area tailoring. Advanced source/drain epitaxial replacement techniques and uniform threshold voltage control through dummy nanosheet layers are among their key innovations.
Institute of Microelectronics, Chinese Academy of Sciences
The Institute has developed GAA transistor technologies focused on material engineering and novel channel architectures. Notable innovations include n-channel and p-channel GAA transistors with differentiated germanium content — where p-channel devices feature higher Ge content in gate-covered channel portions — and the use of graphene nanosheets in a nanosheet GAA transistor to address low mobility and conductivity issues. The Institute has also developed nanowire/nanosheet devices with integrated support portions for enhanced mechanical stability and stacked nanosheet GAA FETs with air gap spacer layers.
Track patent filings from Samsung, TSMC, IBM, and emerging Chinese players in real time with PatSnap Eureka’s competitive intelligence tools.
Monitor GAA Competitors in PatSnap Eureka →Future Pathways: Stacked Channels, Hybrid Platforms, and Advanced Isolation
Three innovation pathways are shaping the next generation of GAA transistor development beyond 2026: advanced nanosheet scaling with stacked channel architectures, hybrid MBCFET-nanosheet integration platforms, and next-generation forksheet technology with advanced isolation.
Advanced Nanosheet Scaling with Stacked Channel Architecture
This pathway focuses on multi-stacked nanosheet GAA transistors with optimised channel width and thickness scaling for continued Moore’s Law progression beyond 2nm nodes. Key developments include advanced epitaxial growth techniques for uniform nanosheet formation, novel spacer materials for improved electrostatic control, and high-mobility channel materials like SiGe. The stacked architecture allows for increased drive current per footprint while maintaining short-channel control. Manufacturing considerations include thermal budget management, stress engineering for mobility enhancement, and yield optimisation through defect reduction. The PatSnap R&D intelligence platform tracks over 2 billion data points across global patent filings in this space.
Hybrid MBCFET-Nanosheet Integration Platform
This approach combines MBCFET and nanosheet architectures within a single technology platform, enabling optimised device selection based on specific circuit requirements. MBCFET devices would serve high-performance logic applications requiring maximum drive current, while nanosheet devices handle power-efficient applications demanding superior electrostatic control. The platform shares process modules — gate stack formation, contact metallisation, and interconnect layers — while maintaining device-specific optimisation steps. Advanced design-technology co-optimisation (DTCO) methodologies enable circuit designers to select optimal device types for different functional blocks within the same chip.
Next-Generation Forksheet with Advanced Isolation Technologies
This pathway focuses on breakthrough isolation techniques using ultra-low-k materials and air-gap technologies to minimise inter-device coupling. Key advances include selective area deposition for precise dielectric placement, novel etching processes for controlled air gaps, and machine learning-driven process optimisation for uniform isolation across large wafer areas. Advanced forksheet designs feature optimised fin pitch scaling, improved source/drain contact resistance through novel silicide technologies, and enhanced gate workfunction engineering for multi-threshold applications. The technology platform enables aggressive area scaling while addressing the fundamental isolation and manufacturing challenges that currently limit forksheet adoption.
MBCFET technology enables easy migration from FinFET manufacturing by reusing 90% or more of existing FinFET processes, requiring only a few revised masks, which significantly reduces capital expenditure and accelerates time-to-market for GAA transistor production.
Across all three pathways, cost and yield optimisation remain central concerns. Variable nanosheet width optimisation allows standard cell design improvements while enabling effective capacitance, resistance, and frequency modulation through effective width control. The development of uniform single-crystalline 2D high-κ dielectric/semiconductor heterostructures for scalable batch synthesis represents a significant advancement in industrial GAA manufacturing, addressing contamination-free contact requirements while maintaining atomic-scale interface quality. Semiconductor industry standards bodies including SEMI are actively developing equipment and materials specifications to support these next-generation process requirements.