Why FinFET Failed and How GAA Solves It

Gate-All-Around (GAA) nanosheet transistors replace FinFETs at the 2nm node because FinFET’s three-sided gate can no longer prevent the drain’s electric field from penetrating the channel at gate lengths below approximately 7nm — a failure mode known as drain-induced barrier lowering (DIBL). The GAA architecture directly eliminates this by enclosing each channel region with gate dielectric and gate metal on all four sides simultaneously, maximising gate-to-channel coupling and suppressing off-state leakage at the dimensions required for 2nm-class CMOS.

The dominant technical approach across the field is the horizontally stacked nanosheet FET — thin semiconductor ribbons suspended above the substrate and completely encircled by a metal gate. Samsung Electronics’ foundational patent formally defines the key geometry: a unitary gate material completely surrounding the horizontal nanosheet conductive channel, with width defined by the physical channel width and source/drain regions at opposing ends.

In a 2nm-node GAA device, the transistor is built not from a single nanosheet but from a vertical stack of 3–4 suspended silicon nanosheets, each acting as an independent parallel conduction channel. The gate metal wraps continuously around every nanosheet in the stack, meaning the effective channel width scales as N × (nanosheet width) within the same footprint that previously held a single FinFET fin. As described in Qualcomm’s published patent on variable vertical-stack nanosheet devices, a baseline GAA technology includes a fixed nanosheet count where all N nanosheets function as channels — this multiplicative channel width is precisely what gives GAA its drive current advantage over FinFET at equivalent die area.

Huawei’s PCT application on nanosheet-based devices states the comparison explicitly: compared to a FinFET, GAA nanosheet transistors may deliver more drive current due to an increased channel width in the same circuit footprint, and the GAA design may improve channel control and may minimise short-channel effects. The same application also highlights a persistent scaling challenge: a high aspect ratio (width/thickness greater than 4) causes the device to behave more like a dual-gate structure than a true all-around device, placing a practical limit on how aggressively gate length can be scaled.

The Fabrication Sequence That Makes Nanosheets Possible

GAA nanosheet fabrication begins with the growth of an alternating epitaxial superlattice of silicon and silicon-germanium on a silicon substrate — the Si layers become the channel nanosheets, while the SiGe layers are sacrificial and will be selectively removed later to suspend the sheets in free space. Every subsequent process step in the front-end-of-line (FEOL) sequence is designed to release, protect, and ultimately gate those suspended ribbons with nanometre precision.

Epitaxial Superlattice Growth and Raman Metrology

IBM Research’s manufacturing paper on in-line Raman spectroscopy for GAA device manufacturing describes the use of fully strained pseudomorphic Si(1−x)Ge(x) layers with germanium content x = 0.25, 0.35, or 0.50 grown on a Si substrate. In-line Raman spectroscopy is used throughout FEOL processing to track compositional and strain evolution of both Si and SiGe nanosheets — a critical metrology step for yield control at this scale. Separately, the Institute of Microelectronics of the Chinese Academy of Sciences has patented a nanosheet GAA transistor using graphene nanosheets as channel material, where graphene nanosheet stacks form the plurality of conductive channels surrounded by the all-around gate.

Inner Spacer Formation: The Structural Element Unique to GAA

After the SiGe sacrificial layers are selectively etched to release the suspended Si nanosheets, a process step with no FinFET equivalent becomes critical: inner spacer formation. IBM’s heavily cited patent on gate spacer and inner spacer formation for nanosheet transistors (76 citations) describes how inner spacers are formed in the spaces between channel nanosheets using the same conformal spacer material as the outer gate spacer. These inner spacers electrically isolate the gate metal from the source/drain epitaxial regions — essential at the sub-10nm contacted poly pitch (CPP) dimensions of the 2nm node, where even a few nanometres of gate-to-drain overlap would create unacceptable parasitic capacitance.

IBM’s related patent on nanosheet MOSFETs with asymmetric threshold voltage discloses an advanced inner spacer variant: a protruding T-shaped inner spacer on one side of the nanosheet stack physically pinches off the metal gate stack, creating asymmetric threshold voltages. This is a key technique for multi-Vt libraries without requiring different gate metal compositions in every transistor — a significant simplification of the process integration challenge.

Source/Drain Contact Resistance: The Dominant Parasitic at 2nm

Once the nanosheets are released and the metal gate is filled, contact resistance at the source/drain becomes one of the most critical parasitics. Applied Materials has filed a globally-deployed patent family addressing this directly: their method deposits a selective silicide layer at the sidewalls of each nanosheet channel via a silicidation process before performing metal fill, with the metal extending from the lowermost to above the uppermost nanosheet channel. This wrap-around contact geometry maximises contact surface area at each Si channel end, directly reducing source/drain contact resistance. IBM’s wraparound contact patent further demonstrated a V-shaped internal recess in the source/drain region, enabling the contact to wrap the epitaxial material from the front, rear, and internal recess surfaces simultaneously.

Electrostatic Superiority: Quantifying the GAA Advantage

GAA outperforms FinFET at the 2nm node because the gate electric field surrounds the entire perimeter of each nanosheet, maximising gate-induced charge inversion and minimising DIBL — and this advantage has now been quantified in peer-reviewed literature. The comparative analysis by Kakushima and Wong (Tokyo Institute of Technology / City University of Hong Kong, 2022) establishes the scaling conditions under which vertically stacked nanosheet (VNSFET) structures outperform FinFET: the nanosheet structure has advantages specifically when the intersheet spacing or vertical sheet pitch is less than the sheet width, and the minimum intersheet/interwire spacing — set by gate oxide and metal gate thicknesses — must be in the 7–8 nm range at advanced nodes.

“Compared to a FinFET, GAA nanosheet transistors may deliver more drive current due to an increased channel width in the same circuit footprint, and the GAA design may improve channel control and may minimise short-channel effects.”

A Samsung Electronics joint study with Konkuk University (2021) showed at the device–circuit co-optimisation level that a multi-nanosheet FET with a bottom oxide (bottom dielectric isolation) significantly improves subthreshold swing (SS) and DIBL compared to devices without this feature, while also improving both power and performance at the circuit level. According to IEEE standards for transistor characterisation, subthreshold swing and DIBL are the two primary figures of merit for short-channel electrostatic control — both of which GAA with bottom dielectric isolation improves simultaneously.

Fudan University researchers proposed source/drain (S/D) trimming to reduce parasitic RC — enabling a 27.8% ring-oscillator delay improvement in 3-layer stacked GAA devices, and pointing toward 4+ layer nanosheet stacks as a technology extension beyond 3nm CMOS. However, thermal constraints temper this scaling path: Chinese Academy of Sciences researchers showed that as the number of lateral stacks increases beyond 4, thermal crosstalk between nFET and pFET devices degrades performance and must be accounted for in circuit-level design. This finding — published in 2023 and reported by researchers at the Chinese Academy of Sciences — establishes a practical upper bound on nanosheet stack count without active thermal management.

Multi-Threshold Voltage Engineering and the CFET Frontier

Modern 2nm-node standard-cell libraries require multiple threshold voltage (multi-Vt) flavours — low-Vt for high performance, high-Vt for low leakage — and achieving these without area penalty is one of the central integration challenges of GAA. The dominant mechanism, confirmed by IMEC’s experimental work on metal gate work function engineering, is dipole formation at the metal/high-k and high-k/SiO₂ interfaces, which is responsible for effective work function shifts in high-k/metal gate (HKMG) stacks.

Inner/Outer Gate Work Function Mismatch

Huawei and IMEC jointly filed a patent for a GAA device featuring work function mismatch between inner and outer gates, in which inner gate metal layers (1–2 nm thick) and outer gate metal layers (5–7 nm thick) are fabricated from different work function metal (WFM) compositions. The functional work function difference between them is controlled to ±250 meV, enabling threshold voltage tuning without increasing the cell footprint. This architecture also enables more aggressive vertical spacing reduction between channel layers, allowing the addition of more nanosheet layers within the same fin height.

IBM’s stacked nanosheet ROM patent extends multi-Vt to non-volatile memory by integrating a lower nanosheet stack with a first WFM and an upper nanosheet stack with a second WFM — yielding two distinct threshold voltages in a single 3D footprint. This demonstrates that the same work function engineering principles that enable logic multi-Vt can be extended to embedded memory at the 2nm node.

Complementary FET (CFET): nFET Over pFET

The next major evolution beyond standard GAA is the Complementary FET (CFET), in which an nFET nanosheet transistor stack is fabricated directly on top of a pFET stack within the same gate structure, dramatically reducing standard cell area. According to IMEC‘s published roadmaps, CFET is the primary technology pathway for area scaling beyond the 2nm node. Intel has filed a patent for a Ribbon CFET multi-voltage threshold integration architecture, describing a stacked CFET where the first (lower) transistor layer and second (upper) transistor layer each contain multiple channel ribbons surrounded by individual metal gate stacks with different combinations of N- and P-dipole doses — enabling multi-Vt without area penalty.

IBM has filed a CFET foundation patent for self-aligned hybrid substrate stacked gate-all-around transistors, demonstrating vertically stacked nFET/pFET nanosheet structures on different crystalline orientations: Si (100) orientation for the top transistor (nFET, maximising electron mobility) and Si (110) orientation for the bottom transistor (pFET, maximising hole mobility). Samsung Electronics additionally patented 3D-stacked semiconductor devices with different channel layer intervals, where the lower nanosheet transistor uses a smaller channel interval (tighter sheet pitch) than the upper transistor — a deliberate asymmetry to optimise performance trade-offs between the two stacked devices.

Patent Landscape: Who Is Driving GAA Innovation?

Global patent and academic databases contain over 5,400 combined hits for GAA nanosheet devices, with dominant activity concentrated at a small number of organisations whose innovation focus areas are distinct and largely complementary. Based on the combined patent and literature analysis, eight organisations account for the majority of foundational filings.

IBM Research Albany stands out for breadth of innovation across the full GAA integration stack — from fundamental nanosheet release processes to multi-Vt engineering, stacked memory integration, and wraparound contact structures. According to WIPO‘s patent filing statistics, semiconductor process patents of this type typically take 18–24 months from priority date to publication, meaning the most recent filings in this landscape represent R&D from 2022–2023. Samsung has the largest total volume of GAA patents reviewed, covering fundamental structure patents with high citation counts. Intel’s recent filings are notably forward-looking, emphasising CFET and machine-learning-guided process control for variability management.

Academic research in this space is especially concentrated at IBM Research Albany, Samsung’s semiconductor R&D centres, IMEC (Leuven), and Fudan University. The geographic concentration of foundational patents at US, Korean, and Belgian institutions reflects the capital-intensive nature of advanced CMOS process R&D — a pattern consistent with broader semiconductor innovation trends tracked by the OECD in its technology and innovation outlook reports.

Qualcomm’s variable vertical-stack patent introduces a commercially significant dimension: rather than fixing nanosheet count across an entire chip, Qualcomm describes circuits in which different transistor instances use different stack heights, enabling a single process to deliver both high-performance (more sheets, more drive current) and low-power (fewer sheets, reduced capacitance) transistors on the same die. This directly addresses the mixed-performance requirements of modern SoC design — a capability that the PatSnap IP intelligence platform can help R&D teams map across the full competitive landscape.