GaN-on-Si breakdown voltage: 6 ways to reach 1700 V

The thickness trap: why more buffer is not the answer

The dominant approach to raising GaN-on-Si breakdown voltage has been to grow a thicker buffer—but this directly worsens the thermal path to the substrate. GaN buffer thermal conductivity is approximately 130 W/m·K at room temperature, and each additional micrometer of epitaxial material adds roughly 0.08 K·mm/W of thermal resistance, while GaN/Si interface resistance already contributes 10–30 m²K/GW. For power conversion applications where junction temperatures are tightly constrained, that trade-off is unacceptable.

The fundamental insight driving modern GaN-on-Si engineering is that breakdown voltage is determined by electric field distribution, not simply by epitaxial thickness. Intelligent management of that distribution—through buffer composition, termination structures, and device geometry—can achieve breakdown voltages of 1000–1700 V with buffer thicknesses of only 6–9 μm, significantly thinner than the 12–15 μm required by traditional approaches. According to research tracked by WIPO, wide-bandgap power semiconductor patents have grown rapidly as the industry seeks exactly this kind of performance-per-thickness improvement.

The strategies that follow are not theoretical. Each is backed by published research or granted patents, and each operates within a fixed thermal budget by changing how the electric field is distributed rather than how much material is grown.

Superlattice buffer engineering: thin layers, higher fields

Superlattice buffer structures improve breakdown voltage by creating controlled potential barriers that distribute the electric field more uniformly throughout the buffer—without adding bulk thickness. Three distinct architectures have demonstrated measurable results.

Reverse-stepped superlattice layers

GaN-on-SOI substrates with reverse-stepped superlattice (SL) layers achieve 750 V breakdown voltage with only a 9 μm total buffer thickness. The reverse-stepped design gradually varies layer thickness and composition across the structure, creating asymmetric barrier heights in the AlGaN/AlN or AlGaN/GaN layer pairs that provide superior charge management compared to uniform superlattices. This same structure achieves only 450 V on bulk Si, demonstrating that the superlattice and substrate work in concert.

AlGaN/AlN superlattice systems targeting 1 kV

For applications targeting 1 kV buffer breakdown, AlGaN/AlN superlattice systems achieve this milestone with 10–20 periods of AlGaN/AlN pairs, individual layer thicknesses of 5–15 nm, aluminum composition graded from 15–30% in the AlGaN layers, and a total superlattice thickness of only 200–400 nm. The superlattice simultaneously acts as a strain-relief mechanism and a vertical field spreader. The periodic potential barriers create mini-bands that distribute carriers and prevent premature breakdown, while the thin individual layers minimise lattice mismatch stress accumulation.

Strained layer superlattice as drift layer

The most direct substitution replaces the conventional uniform drift layer with a strained layer superlattice (SLS) structure of alternating 3–8 nm layers of GaN and InGaN or GaN and AlGaN. Built-in strain at each interface creates polarization-induced electric fields that counteract the applied reverse bias, spreading the depletion region more uniformly. This technique enhanced breakdown voltage from approximately 450 V to 639 V in fully-vertical GaN-on-Si p-n diodes without changing total epitaxial thickness. The SLS maintains the same thermal resistance as a uniform drift layer of equivalent total thickness.

Advanced edge termination: where most devices actually break down

Edge termination is often the binding constraint on breakdown voltage—more restrictive than bulk breakdown—because electric field crowding at the junction periphery triggers avalanche before the drift region is fully utilised. Three approaches address this without altering the epitaxial stack.

Hydrogen-plasma guard rings

Hydrogen-plasma based guard rings eliminate mesa etching and field plates entirely. Metal rings serve as self-aligned masks during hydrogen plasma exposure; annealing at 400°C then creates stable Mg-H complexes that passivate the p-GaN, converting it into a highly resistive guard ring region. Devices with 10 hydrogen-plasma guard rings achieved 1.70 kV breakdown with only a 9 μm drift layer, reaching a critical electric field of 3.43 MV/cm—close to the theoretical GaN limit. Specific on-resistance remained at 0.65 mΩ·cm², confirming that the breakdown improvement did not compromise conduction performance. The hydrogenated regions remain thermally stable up to 300°C.

“Devices with 10 hydrogen-plasma guard rings achieved 1.70 kV breakdown with only a 9 μm drift layer, reaching a critical electric field of 3.43 MV/cm—close to the theoretical GaN limit.”

Negative fixed charge edge termination

Materials such as Al₂O₃ or Si₃N₄ with engineered fixed charge density create a virtual guard ring effect without physical etching or doping. Negative fixed charge densities in the range of 1–5 × 10¹² cm⁻² significantly reduce peak electric fields at the junction edge by redistributing the field away from the vulnerable junction periphery. This technique is particularly effective for vertical GaN Schottky devices and can be combined with other termination methods for synergistic effects, as documented in research published through IEEE.

Seal ring charge extraction for vertical FinFETs

Vertical GaN FinFET devices face a distinct problem: negative charge accumulation at the edge termination degrades breakdown voltage over time. Seal ring structures with charge extraction capability address this by providing metal seal ring pads that conduct accumulated charge from the edge termination directly to the drain metallization, with p-GaN or insulation layers electrically connected to the scribe line and gate metal contacts that actively extract charge. This prevents leakage current increase and breakdown voltage degradation without adding thermal resistance.

Field plate designs that redistribute lateral electric fields

Field plates reshape the lateral electric field profile in GaN HEMTs and vertical devices without touching the epitaxial structure. The performance gains are substantial and the thermal impact is negligible.

Multi-layer field plate structures

Advanced designs employ multiple field plate layers at different vertical positions: source-connected field plates extending over the gate-drain region, gate-connected field plates integrated with the gate structure, and floating field plates that redistribute field through capacitive coupling. Simulation studies demonstrate that optimised triple field plate structures (gate FP + source FP + drain FP) can increase breakdown voltage by 40–60% compared to devices without field plates, with the epitaxial structure unchanged. The key is optimising the length, thickness, and dielectric spacing of each plate to create a more uniform lateral electric field distribution.

Graded AlGaN field plate structures

A thin graded p-type AlGaN layer of 125 nm or less, combined with a p-GaN cap layer of 50–300 nm, creates charge separation through polarization-induced 2D carrier gases. A two-dimensional hole gas (2DHG) forms at the AlGaN/GaN heterojunction while a two-dimensional electron gas (2DEG) forms at the drift layer/AlGaN interface. The graded AlGaN field plate achieves breakdown voltages exceeding 1000 V without requiring thick graded drift regions, with aluminum composition grading from 10–20% at the bottom to 0% at the top. The thin field plate adds negligible thermal resistance compared to bulk buffer thickness increases.

Quasi field plates

Quasi field plates use existing device metallization layers (source, gate) extended laterally with optimised dielectric thickness and geometry—no additional mask layers required. By carefully designing overlap distances and dielectric thicknesses, quasi field plates provide 20–30% breakdown voltage improvement with minimal process complexity and no impact on thermal resistance.

Carbon doping and substrate engineering

Carbon doping profile and substrate choice each offer independent levers for breakdown voltage improvement that operate entirely outside the active device epitaxy.

Optimised carbon doping profiles

Vertical breakdown voltage in GaN-on-Si correlates strongly with carbon doping uniformity. Devices with optimised graded carbon profiles—higher near the Si interface (5–10 × 10¹⁸ cm⁻³), lower near the channel (1–3 × 10¹⁸ cm⁻³), and with the top 500–1000 nm of the buffer kept carbon-free—achieve 30–50% higher breakdown voltage compared to uniformly doped buffers of the same thickness. The carbon-free top region avoids trap-related current collapse and breakdown degradation. Precise flow control of CCl₄, CBr₄, or propane precursors during MOCVD growth is required to maintain the profile.

An alternative architecture uses alternating carbon-doped (100–300 nm) and undoped GaN layers (200–500 nm) within the buffer—3 to 5 alternating layers within the same total buffer thickness. Breakdown voltage improvements of 15–25% have been reported compared to uniformly doped buffers, as tracked in research cited by Nature Electronics and related journals.

SOI and partial substrate removal

Replacing bulk Si with SOI substrates provides a buried oxide (BOX) layer that acts as an additional dielectric barrier, preventing leakage through the substrate. GaN-on-SOI devices demonstrate 750 V breakdown with the same epitaxial structure that achieves only 450 V on bulk Si. Careful engineering of BOX thickness (typically 200–400 nm) and thermal vias maintains acceptable thermal performance. For cost-sensitive applications, even partial substrate removal beneath the active area can increase breakdown voltage by 30–100% depending on the extent of removal, by eliminating the parasitic substrate conduction path.

Heterogeneous substrate bonding

Substrate transfer to high thermal conductivity materials (SiC, diamond, or Cu) after GaN-on-Si growth maintains the optimised epitaxial structure while replacing the limiting substrate. Devices fabricated this way can achieve breakdown voltages 2–3× higher than equivalent structures on Si, while simultaneously improving thermal resistance by 30–50% due to the superior thermal conductivity of the replacement substrate. The approach is referenced in patent filings tracked by EPO for GaN power device substrate engineering.

Vertical device architectures and how to combine strategies

Vertical GaN device architectures exploit the full drift layer thickness for voltage blocking, whereas lateral devices use only a fraction of the buffer thickness for breakdown support—making the architecture choice itself a multiplier on all other strategies.

Fully vertical and quasi-vertical structures

Fully-vertical GaN-on-Si MOSFETs with localised epitaxial growth demonstrate 402 V breakdown with drift layers under 5 μm. Combined with optimised edge termination, vertical structures can achieve 3–4× higher breakdown voltage per unit epitaxial thickness compared to lateral devices. Vertical current flow eliminates lateral field crowding at the gate edge, reduces device footprint for the same current rating, and naturally distributes field through the drift region thickness.

Recommended strategy combinations by voltage target

For 600–800 V applications: a reverse-stepped superlattice buffer (200–300 nm total SL thickness), hydrogen-plasma guard rings (5–7 rings), single or dual field plates, and an optimised carbon doping profile. For 1000–1500 V applications: an AlGaN/AlN superlattice buffer (300–400 nm), negative charge edge termination, a triple field plate structure, SOI or partial SOI substrate, and a vertical or quasi-vertical device architecture. For applications above 1500 V: a strained layer superlattice drift region, multiple combined edge termination techniques, a graded AlGaN field plate structure, substrate replacement or bonding, and a fully vertical architecture.

Process integration requirements

Successful implementation across all tiers requires precise MOCVD control for superlattice and graded structures, minimised and optimised regrowth interfaces, careful thermal budget management across multiple high-temperature steps, and edge termination and field plate processes compatible with standard device fabrication. The PatSnap R&D intelligence platform provides patent landscape analysis and literature mapping to help engineering teams navigate these process trade-offs efficiently.

“Breakdown voltage is determined by electric field distribution, not simply by epitaxial thickness—and intelligent engineering of that distribution enables dramatic performance improvements within fixed thermal budgets.”

The PatSnap Insights blog tracks ongoing developments in wide-bandgap power semiconductor engineering, including emerging buffer architectures and novel termination structures as they move from research to production. Standards bodies such as IEEE continue to publish benchmarking data that contextualises device-level results within broader power electronics performance roadmaps.