How interface traps drive threshold voltage instability in GaN MIS-HEMTs

Interface trap density at the gate dielectric/GaN boundary is the primary physical parameter governing both the magnitude and the direction of threshold voltage (V_TH) instability in GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Trap states at this boundary capture or emit charge carriers under varying gate bias conditions, modulating the effective charge in the channel and shifting the electrostatic condition at which the two-dimensional electron gas (2DEG) forms. Reported D_it values span a wide range — from approximately 2×10¹⁰ cm⁻² eV⁻¹ to above 3×10¹³ cm⁻² at nitride/GaN interfaces — and the position of a given device within this range directly determines the severity of its V_TH transient behaviour during power switching.

As reviewed by the Slovak Academy of Sciences (2020), bias-temperature instabilities (BTI) in both depletion- and enhancement-mode GaN MIS-HEMTs are primarily associated with the distribution of defect states in the gate dielectric volume and at the dielectric/GaN interface. Both the density and energetic distribution of interface traps are critical parameters — not simply their total count. This finding, consistent across more than 20 peer-reviewed studies, establishes that any engineering strategy targeting V_TH stability must address D_it as its first-order variable, in line with broader reliability frameworks described by organisations such as IEEE for wide-bandgap power devices.

The direction of V_TH shift follows a well-understood physical logic: under positive gate stress, interface traps capture electrons, and the resulting trapped negative charge partially depletes the 2DEG, producing a positive V_TH shift. Under negative gate bias, previously filled traps emit electrons, causing the opposite drift. This bidirectionality means that the same device can exhibit both positive and negative V_TH excursions within a single switching cycle, depending on the instantaneous gate waveform — a critical reliability consideration for power conversion circuits operating at high frequency.

The spatial location of traps within the gate stack adds a further dimension. Research from STMicroelectronics (2022) on fully recessed MIS-gate GaN transistors demonstrated that V_TH relaxation after voltage stress is primarily governed by charges residing near the gate dielectric/GaN interface — specifically within the dielectric itself or the GaN epitaxial layer immediately beneath the oxide. That study distinguished between fast interface traps and slower bulk dielectric traps, both contributing to transient instability during power switching. In semi-vertical GaN-on-Si trench-MOSFETs studied at the University of Padova (2020), small negative V_TH shifts at low stress were attributed to trapping within the insulator, while positive V_TH shifts at high stress were attributed to trapping at the metal/insulator interface — illustrating that bias level determines which trap population dominates.

“The density and energetic distribution of interface traps are critical parameters — not simply their total count. Any engineering strategy targeting V_TH stability must address D_it as its first-order variable.”

A TCAD study from Asia University (2021) on 600 V GaN/AlGaN/GaN devices provided precise numerical grounding: threshold voltage is set by donor-like traps at nitride/GaN interfaces at a density of approximately 3×10¹³ cm⁻² with an energy 1.42 eV below the conduction band, alongside acceptor traps in the AlGaN layer and buffer regions with an activation energy of 0.59 eV. These parameters directly determine the equilibrium V_TH and govern its sensitivity to subsequent charge redistribution under stress — providing a quantitative foundation for TCAD-guided device design, as increasingly supported by OECD frameworks for semiconductor technology roadmapping.

Measuring D_it: quantitative methods and reported values in GaN gate stacks

Quantitative characterisation of interface trap density is essential for correlating D_it to V_TH instability severity, yet the range of applicable techniques and the complexity of overlapping trap states make this a non-trivial measurement challenge. A 2023 critical review from Shanghai University surveyed the full range of applicable methods, comparing techniques for bulk versus interface trap characterisation including capacitance-voltage (C-V), conductance-voltage (G-V), deep-level transient spectroscopy (DLTS), and drain current transient analysis — each sensitive to different trap populations and energy ranges within the GaN bandgap.

The most rigorous quantitative study in the dataset comes from King Saud University (2021), which measured interface state densities of 2×10¹⁰ cm⁻² eV⁻¹ with a time constant of 1 µs using capacitance-frequency measurements, and resolved the four distinct deep trap levels noted above using DLTS. The presence of multiple overlapping trap states complicates the V_TH transient response: each trap level produces a characteristic emission time constant that contributes to the overall slow V_TH recovery observed after gate stress in GaN power HEMTs. This multi-exponential behaviour means that single-time-constant models systematically underestimate the duration of V_TH instability — a point with direct implications for power converter control loop design.

At the AlGaN/GaN heterointerface, the University of Ulsan (2021) extracted a minimum D_it of 2.5×10¹² cm⁻² eV⁻¹ using the conventional conductance method on FATFET structures. This value was shown to be consistent with a subthreshold swing of approximately 142 mV/decade measured in actual transistors, directly linking extracted D_it to a measurable device electrical parameter accessible without specialised equipment. Border traps extending into the barrier were also characterised, highlighting the need to distinguish interface states from near-interface bulk traps when modelling V_TH instability — a distinction that is often conflated in simpler analytical models.

UV-assisted C-V analysis, applied by the University of Padova (2020) to semi-vertical GaN-on-Si trench-MOSFETs, provided a complementary approach: de-trapping threshold energies of approximately 2.95 eV were extracted, and the technique directly characterised the GaN/Al₂O₃ interface state distribution. This measurement approach is particularly valuable for distinguishing between traps of different energetic depths, since shallow traps respond to UV illumination at lower photon energies than deep traps — enabling a spatially and energetically resolved picture of the interface trap landscape that is not achievable by electrical measurements alone.

The need for standardised measurement protocols has become a recognised gap in the field. The “Triple Sense” protocol, developed at Univ. Lyon (2023) by adapting SiC MOSFET qualification methods to GaN HEMTs, addresses the fact that interface-trap-induced transient V_TH shifts corrupt conventional threshold voltage readings. Without accounting for the transient nature of D_it-driven instability, V_TH measurements taken at different sweep rates or delay times yield different values for the same device — making cross-laboratory comparison unreliable and complicating qualification for power applications. This standardisation effort reflects growing recognition, also noted in IEC working groups on wide-bandgap device qualification, that measurement methodology must evolve alongside device technology.

Architecture and process effects: how gate stack design determines V_TH sensitivity

The gate architecture fundamentally shapes how interface trap density translates into V_TH instability, because different gate stack configurations introduce different trap populations at different interfaces. The three dominant architectures in GaN power devices — p-GaN Schottky gate, MIS-HEMT with a deposited gate oxide, and fully recessed MOSFET-channel HEMT — each exhibit distinct V_TH instability signatures that reflect the specific trap species and interface locations present in each stack.

p-GaN gate devices: nitrogen and gallium vacancy traps

In p-GaN gate devices, the metal/p-GaN/AlGaN/GaN stack introduces multiple charge trapping interfaces. Research from CNR-IMM Catania (2022) demonstrated that under on-state stress, both electron and hole trapping occur at distinct interfaces depending on gate bias level: electrons are trapped for gate voltages below 6 V (causing positive ΔV_TH), and holes are trapped for gate voltages above 6 V (causing negative ΔV_TH). Activation energies extracted from temperature-dependent gate current measurements identified the electron traps as nitrogen vacancies and the hole traps as gallium vacancies in the p-GaN layer — providing a direct link between specific point defect chemistry and the polarity of V_TH instability.

Temperature is a critical aggravating variable for interface-trap-driven V_TH instability in p-GaN devices. Research from Nanjing University (2022) systematically investigated Schottky gate (SG) and Ohmic gate (OG) p-GaN devices under temperature-dependent negative gate bias stress. For SG devices, a concave-shaped V_T evolution emerged with increasing temperature, while OG devices showed qualitatively different thermal behaviour due to differing trap emission kinetics. This temperature dependence confirms that D_it-driven V_TH instability worsens in high-temperature power applications — a reliability concern directly relevant to automotive and industrial power conversion where junction temperatures routinely exceed 150 °C.

MIS-HEMT architectures: oxide-induced interface states

In MIS-HEMT architectures, the presence of a gate oxide introduces additional interface states not present in Schottky or p-GaN gate devices. Research from National Chiao-Tung University (2017) showed that under high applied electric fields, traps at the dielectric/III-N barrier interface and within the III-N barrier cause both dynamic on-resistance increase and V_TH shift. Stress under off-state conditions — including V_DS = 0 V, off-state, and cascode-connection configurations — revealed that the dielectric interface trap population grows under repeated high-field stress, progressively worsening V_TH stability over device lifetime. This trap generation under stress, distinct from pre-existing D_it, represents a degradation mode that cannot be fully characterised by initial D_it measurements alone.

Fully recessed MIS-gate structures: etch-induced defects

For fully recessed MIS-gate GaN-on-Si transistors, CEA-Leti (2023) identified mandatory AlGaN barrier etching as a primary source of etching-related defects, roughness, and interface traps that lead to unstable V_TH and reduced electron mobility. The etching process used to recess the AlGaN barrier down to the GaN channel introduces surface damage and chemical contamination that elevates D_it at the subsequently deposited dielectric/GaN interface — often irreversibly. This review identifies selective etch chemistries, in-situ passivation, and dielectric optimisation as the key process innovations required to suppress etch-induced D_it and achieve stable V_TH in commercial GaN power switches, consistent with WIPO-tracked patent trends showing accelerating activity in selective GaN etch and passivation methods from 2020 onwards.

Carbon doping in the GaN buffer introduces a further indirect coupling mechanism. The University of Modena and Reggio Emilia (2020) used numerical device simulations to show that carbon-related acceptor traps in the GaN buffer attract free holes to the device surface under negative gate bias, where they are captured into interface traps or recombine with gate-injected electrons. This carbon-to-interface trap coupling means that buffer design choices — specifically the carbon concentration profile — directly influence gate dielectric interface trap behaviour and hence V_TH stability, making device optimisation a multi-layer challenge that cannot be addressed by gate stack engineering alone.

Mitigation strategies, innovation trends, and the path to stable V_TH

Reducing interface trap density through process engineering is the most direct and experimentally validated route to V_TH stabilisation in GaN MIS-HEMTs. The most quantitatively rigorous demonstration in the dataset comes from NaMLab/TU Dresden (2020): applying O₂ plasma surface preconditioning before atomic layer deposition of Al₂O₃, followed by N₂ post-metallization annealing, reduced D_it at the Al₂O₃/GaN interface to the order of 2×10¹² cm⁻² eV⁻¹, with a corresponding measurable improvement in V_TH stability under positive gate bias stress. This result establishes the causal chain between D_it reduction and V_TH stabilisation through controlled experimental comparison — not merely correlation.

Hokkaido University’s 2018 review of dielectric materials for GaN MIS-HEMTs identified in-situ SiNx deposition and surface oxidation of (Al)GaN as achieving the best combination of DC performance and stable V_TH among the dielectric options surveyed — including Al-based oxides, SiNx, SiO₂, and high-k dielectrics. Nanolaminate gate dielectric structures were highlighted as a particularly promising design approach, combining the interface quality advantages of thin in-situ layers with the bulk dielectric properties of thicker deposited oxides. The review also identified interface-trap-induced sudden current saturation under forward gate bias as a distinctive failure mode in GaN MIS-HEMTs — directly attributable to D_it magnitude and distinct from the gradual degradation seen in silicon MOSFETs.

The research landscape is dominated by a small number of highly productive groups. The University of Padova has produced the most prolific body of work, spanning p-GaN gate trapping, off-state and on-state stress mechanisms, semi-vertical GaN trench-MOSFET V_TH instability, and buffer trapping kinetics across multiple publications from 2018 to 2021. The University of Modena and Reggio Emilia contributes TCAD-based investigations of carbon-doped GaN MIS-HEMTs, including the carbon/interface trap coupling study and the hole redistribution model for R_ON transients. STMicroelectronics provides the analytical V_TH recovery model for fully recessed MIS-HEMTs, while CEA-Leti contributes the most comprehensive review of fully recessed MIS gate technology from a process-engineering perspective.

Notable patent activity from Chinese institutions — including the University of Electronic Science and Technology of China, Beijing University of Technology, and Nanjing-based institutes — focuses on modelling threshold voltage drift as a function of switching frequency and drain-source voltage, and on developing novel trap characterisation methods based on drain-source resistance transients and voltage transient responses. This patent activity signals commercial intent to translate laboratory characterisation methods into production-line qualification tools, a transition that WIPO patent trend data identifies as accelerating since 2021.

The convergence of process optimisation, analytical modelling, and standardised measurement protocols represents the current state of the art. For R&D engineers, the practical implication is clear: achieving stable V_TH in GaN MIS-HEMTs requires simultaneous control of gate dielectric deposition conditions (to minimise initial D_it), etch process chemistry (to avoid introducing etch-induced interface states), buffer carbon doping profile (to decouple buffer trap dynamics from gate interface behaviour), and measurement methodology (to obtain reproducible V_TH values for qualification). No single intervention is sufficient; the multi-layer nature of the challenge, documented across more than 50 sources in this dataset, reflects the fundamental complexity of the GaN/dielectric interface in wide-bandgap power devices — a challenge that continues to drive active research and IP generation at institutions worldwide.