Why High-k/Metal Gates Became Unavoidable for CMOS Scaling

The transition to high-k/metal gate (HKMG) architectures was forced by a fundamental physics limit: as SiO₂ gate oxide thickness falls below approximately 1 nm, direct quantum mechanical tunneling causes exponentially increasing gate leakage current, raising standby power to unacceptable levels. This finding, established in a 2010 Texas State University review of HKMG devices and corroborated by a 2006 SEMATECH gate-stack review citing 140 references, made continued SiO₂ scaling physically untenable.

The solution is to replace SiO₂ with a physically thicker high-k dielectric — most commonly hafnium-based materials — that provides the same or lower equivalent oxide thickness (EOT) while dramatically reducing leakage. Hafnium-based dielectrics, after roughly a decade of intensive research documented by SEMATECH, achieved electrical performance matching conventional SiO₂ at a fraction of the leakage. Simultaneously, polysilicon gates were found to suffer from “polysilicon depletion” — a parasitic capacitance effect that increases effective EOT — making metal gate electrodes a necessary companion to high-k dielectrics, as noted by IBM’s T.J. Watson Research Center in 2006.

The critical challenge introduced by metal gates is work function engineering. As a 2018 review on work function setting in high-k metal gate devices states directly: “In both integration schemes, getting the right work functions and threshold voltages for NMOS and PMOS devices is critical.” This single requirement — setting band-edge work functions independently for both transistor types without destabilising the high-k stack — is the central tension that differentiates gate-first from gate-last process architectures.

Gate-First Integration: Simplicity at the Cost of Thermal Exposure

In gate-first HKMG integration, the high-k dielectric and metal gate are deposited early in the process flow — before source/drain formation, spacer deposition, and the high-temperature anneals (typically 900–1050°C) required to activate dopants. This mirrors the conventional polysilicon gate sequence and is therefore more compatible with existing CMOS manufacturing infrastructure.

A canonical gate-first flow, described in a 2012 patent from the Institute of Microelectronics at the Chinese Academy of Sciences, proceeds as follows: an ultra-thin interfacial oxide or oxynitride is grown by rapid thermal oxidation; a high-k gate dielectric layer is formed by physical vapor deposition (PVD); rapid thermal annealing follows; then a metal nitride gate is deposited by PVD and selectively doped — P-type dopants for PMOS, N-type dopants for NMOS — by ion implantation using photoresist masks. Polysilicon is then deposited as a capping and hardmask layer, and the full gate stack is patterned by lithography and etching. A 2014 update from the same institution reinforces this sequence, describing selective ion implantation into the metal nitride gate to differentiate NMOS and PMOS work functions.

The primary advantage of gate-first processing is simplicity: the gate stack is patterned once, and conventional spacer and source/drain process modules follow without requiring dummy gate formation, chemical mechanical planarization (CMP), or selective gate removal. However, the critical drawback is that high-temperature source/drain annealing can cause interfacial reactions between the metal gate, the high-k film, and the silicon substrate, shifting flat-band voltages and effective work functions in unpredictable ways — a phenomenon sometimes called Fermi-level pinning or work-function roll-off. This makes achieving precise mid-gap or band-edge work functions for both NMOS and PMOS simultaneously very difficult under a single high-thermal-budget gate-first flow.

Gate-first flows remain relevant for emerging channel material integration. A 2022 study from the Nanjing Institute of Technology applied gate-first fabrication to heterogeneous CMOS integrating InGaAs-OI nMOSFETs and Ge pMOSFETs, using a two-step gate oxide strategy — self-cleaning atomic layer deposition for InGaAs and ozone post-oxidation for Ge — and achieved on-currents up to 8.3 µA/µm. This demonstrates that gate-first flows can be viable where source/drain thermal budgets are tailored to be compatible with fragile high-k stacks on alternative channel materials.

Gate-Last (Replacement Gate): Work Function Control at Scale

The gate-last approach — also called the replacement metal gate (RMG) process — inverts the sequence entirely: a sacrificial dummy polysilicon gate is formed first, source/drain regions are implanted and annealed at high temperature using the dummy gate as a mask, and then the sacrificial gate is removed by selective etching. The resulting gate trench is filled with the high-k dielectric and the desired metal gate electrodes. This architecture was commercialized by Intel at the 45 nm node and has since become the dominant approach at leading-edge nodes.

A Texas Instruments patent family spanning US, EP, JP, and WO jurisdictions — with active patents as recently as 2025 — states the motivation directly: “As the geometries for integrated circuits have scaled to smaller and smaller dimensions, polysilicon transistor gates have been replaced with metal gates to enable scaling to continue to smaller dimensions.” The key benefit is that the high-k dielectric and metal gate never see the high-temperature source/drain anneal, giving far greater freedom in selecting metal gate materials with precisely tuned work functions.

“In both integration schemes, getting the right work functions and threshold voltages for NMOS and PMOS devices is critical” — and it is the gate-last approach’s protection of the metal gate from high-temperature steps that makes precise band-edge work function setting achievable in high-volume production.

Work function differentiation in the replacement gate flow is achieved by depositing different metal layers selectively into NMOS and PMOS gate recesses. A 2022 GlobalFoundries patent describes a sophisticated multi-step fill process: a conformal sacrificial metal cap material (SMCM) layer is formed above a high-k gate insulation layer within both NMOS and PMOS replacement gate cavities; the SMCM is selectively removed from one cavity while remaining in the other; a first conformal metal-containing material layer is deposited; that layer is removed from one cavity; and finally a second conformal metal layer fills both cavities — yielding independently programmed work functions for each transistor type. A 2015 GlobalFoundries patent extends this by driving lanthanide-based material into the high-k layer via thermal processing within the gate recesses, further tuning threshold voltages for both NMOS and PMOS without exposing the stack to front-end high temperatures.

EOT scaling in the replacement gate flow presents its own challenges. IBM’s Thomas J. Watson Research Center showed in 2012 that La-based higher-k materials (k > 20) can achieve EOT as low as 0.5–0.8 nm, but with effective work functions suitable primarily for NMOS. Remote interfacial layer (IL) scavenging — reducing the SiO₂ IL thickness by chemical or thermal means after gate stack deposition — can push EOT below 0.5 nm but risks loss of effective work function (EWF) control and severe mobility degradation if the IL is eliminated entirely. These EOT-mobility-EWF trade-offs must be resolved within the replacement gate framework for each successive technology node, according to IBM research.

Hybrid High-k-First/High-k-Last: The Leading Industrial Solution

Recognising that neither purely gate-first nor purely gate-last approaches simultaneously optimise NMOS and PMOS device characteristics, Texas Instruments developed and patented a hybrid integration scheme that applies each approach selectively to the transistor type it best serves. This architectural insight is protected by one of the most extensive HKMG patent families in the dataset, spanning US, EP, JP, WO, and CA jurisdictions with filings starting in 2013 and active protection as recently as 2025.

The invention provides “a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.” The NMOS device benefits from the superior quality of a thermally grown SiO₂ interfacial layer, which improves channel mobility and reduces interface trap density. The PMOS device benefits from the low-temperature replacement gate environment, where the metal/high-k interface can be precisely engineered without work-function roll-off from thermal exposure.

This architectural split exploits a key asymmetry: NMOS performance is more sensitive to the quality of the Si/SiO₂ interface (favouring thermal growth, which gate-first enables), while PMOS work function setting is more sensitive to the metal/high-k interface (favouring the low-temperature replacement gate environment). A Texas Instruments EP patent active through 2026 specifies the work function targets precisely: a thick TiN metal gate with work function greater than 4.85 eV for PMOS replacement gate transistors, and a thin TiN metal gate with work function less than 4.25 eV for NMOS replacement gate transistors.

Gate-Stack Material Engineering and EOT Scaling Limits

Beyond process topology, advanced nodes require careful gate-stack material engineering to maximise the Ion/Ioff ratio and suppress leakage. Samsung Electronics’ 2021 experimental study of a 28 nm low-power HKMG device provides a direct demonstration: by replacing HfSiON with HfSiO thin films and engineering the TiN layer thickness within the gate stack, the electrical oxide thickness was reduced by 3.1% for NFET devices. This improved the Ion/Ioff ratio for a given Ion target while appropriately suppressing gate leakage — all without requiring a full process node change. The finding underscores that sub-layer composition choices within an established gate-last process remain a meaningful performance lever.

At the most aggressive EOT targets, IBM’s 2012 analysis documents that IL scavenging in a replacement gate context — using metal gate capping layers such as TiN atop HfO₂ — can reduce the interfacial SiO₂ layer to sub-angstrom thicknesses, achieving sub-0.5 nm EOT. However, zero-IL conditions introduce severe effective work function instability and channel mobility degradation, underscoring that the replacement gate’s thermal freedom does not eliminate all scaling trade-offs. According to research published by Nature and affiliated journals on semiconductor scaling, the interplay between dielectric quality, mobility, and leakage remains an active area of investigation at every new node.

Integrating embedded non-volatile memory (NVM) alongside HKMG logic transistors introduces further complexity. A 2019 Cypress Semiconductor patent highlights that at 28 nm and beyond, integrating SONOS-type NVM alongside HKMG logic requires significant additions to the mask set and process steps, because the NVM gate stack must be formed before or after the HKMG stack without disrupting either. This integration complexity is typically easier to manage in gate-last flows, where the late-stage gate fill step can be tailored per device type.

Head-to-Head: Key Attributes of Gate-First vs Gate-Last HKMG Integration

The fundamental trade-off between gate-first and gate-last integration can be summarised across eight technical dimensions. Gate-first offers process simplicity and superior thermal SiO₂ interface quality for NMOS, while gate-last provides the work function controllability and EOT scalability required for PMOS and aggressive scaling nodes. The 2018 work function review confirms that both schemes have been implemented in high-volume production, and the dominant direction at leading-edge nodes (sub-22 nm) has been toward gate-last or hybrid architectures because of their superior work function control — as reflected in the breadth of Texas Instruments’ hybrid patent portfolio and GlobalFoundries’ replacement gate process innovations.

The patent data confirms clear assignee concentrations reflecting these trade-offs. Texas Instruments holds the broadest hybrid HKMG portfolio. GlobalFoundries leads in replacement gate multi-work-function innovations. The Institute of Microelectronics at the Chinese Academy of Sciences holds foundational gate-first dual-metal-gate patents from 2012 and 2014. IBM’s T.J. Watson Research Center contributes the most-cited EOT scaling analysis. Samsung provides applied process engineering evidence at 28 nm. SEMATECH, as noted by standards bodies including IEEE, provided influential pre-competitive research that underpins the entire HKMG transition. Together, these players have shaped a technology landscape where gate-last and hybrid architectures dominate at sub-22 nm, while gate-first retains relevance for alternative channel materials and less aggressive thermal budget scenarios.