Why SiO₂/Polysilicon Gates Reached Their Limits

The transition to high-k/metal gate (HKMG) architectures became unavoidable once SiO₂ gate oxide thickness fell below approximately 1 nm: at that point, direct quantum mechanical tunneling causes exponentially increasing gate leakage current, driving standby power to unacceptable levels. This fundamental physics constraint — not a manufacturing limitation — forced the industry to find a replacement dielectric that could provide equivalent or lower capacitive coupling (measured as equivalent oxide thickness, or EOT) while being physically thick enough to suppress tunneling.

The hafnium-based dielectrics that emerged from roughly a decade of intensive research — reviewed by SEMATECH in a 140-reference survey published in 2006 — can match the electrical performance of conventional SiO₂ while dramatically reducing leakage. Polysilicon gates, however, introduced a second problem: “polysilicon depletion,” a parasitic capacitance effect that increases effective EOT. This made metal gates a necessary companion to high-k dielectrics, as documented by IBM T.J. Watson Research Center in 2006.

The critical challenge introduced by metal gates is work function engineering. As a 2018 review of work function setting in high-k metal gate devices states directly: “In both integration schemes, getting the right work functions and threshold voltages for NMOS and PMOS devices is critical.” This is the central tension that differentiates gate-first from gate-last approaches — and it drives the entire patent and process engineering landscape examined here.

Gate-First Integration: Simplicity at the Cost of Thermal Budget

Gate-first integration deposits the high-k dielectric and metal gate early in the process flow — before source/drain formation, spacer deposition, and the high-temperature anneals (typically 900–1050°C) required to activate dopants. This mirrors the conventional polysilicon gate process sequence and is therefore more straightforwardly compatible with existing CMOS manufacturing infrastructure.

A canonical gate-first flow, as described in a 2012 US patent from the Institute of Microelectronics at the Chinese Academy of Sciences, proceeds as follows: an ultra-thin interfacial oxide or oxynitride is grown by rapid thermal oxidation; a high-k gate dielectric layer is formed by physical vapor deposition (PVD); rapid thermal annealing follows; then a metal nitride gate is deposited by PVD and selectively doped — P-type dopants for PMOS, N-type dopants for NMOS — by ion implantation using photoresist masks. Polysilicon is then deposited as a capping/hardmask layer, and the full gate stack is patterned by lithography and etching. A 2014 updated US patent from the same institution reinforces this sequence, describing selective ion implantation into the metal nitride gate to differentiate NMOS and PMOS work functions.

“The threshold voltage of devices is highly dependent on not just the deposited material properties but also on subsequent device processing steps.”

The primary advantage of gate-first processing is simplicity: the gate stack is patterned once, and conventional spacer and source/drain process modules follow. The critical drawback, however, is that the metal gate and high-k dielectric must survive all subsequent high-temperature steps. High-temperature source/drain annealing can cause interfacial reactions between the metal gate, the high-k film, and the silicon substrate, shifting flat-band voltages and effective work functions in unpredictable ways — a phenomenon sometimes called Fermi-level pinning or work-function roll-off. This makes achieving the precise mid-gap or band-edge work functions required for both NMOS and PMOS simultaneously very difficult under a single high-thermal-budget gate-first flow.

Gate-first flows remain relevant for emerging channel material integration. A 2022 study from Nanjing Institute of Technology applied a gate-first fabrication process alongside a two-step gate oxide strategy combining self-cleaning atomic layer deposition for InGaAs and ozone post-oxidation for Ge, achieving on-currents up to 8.3 µA/µm. This illustrates that gate-first processing can be adapted when the thermal budget of source/drain processing is tailored to be compatible with fragile high-k stacks on alternative channel materials.

Gate-Last (Replacement Gate): Precision Through Process Inversion

The gate-last approach — also called the replacement metal gate (RMG) process — inverts the sequence: a sacrificial polysilicon dummy gate is formed first, source/drain regions are implanted and annealed at high temperature using the dummy gate as a mask, and then the sacrificial gate is removed by selective etching. The resulting gate trench is then filled with the high-k dielectric and the desired metal gate electrodes. This was the architecture commercialized by Intel at the 45 nm node.

The key benefit is that the high-k dielectric and metal gate are never exposed to the high-temperature source/drain anneal — they see only relatively low back-end-of-line (BEOL) temperatures — giving far greater freedom in selecting metal gate materials with precisely tuned work functions. A Texas Instruments WO patent from 2015 states the motivation clearly: “As the geometries for integrated circuits have scaled to smaller and smaller dimensions, polysilicon transistor gates have been replaced with metal gates to enable scaling to continue to smaller dimensions.” A 2016 EP version and a 2025 EP active version from the same Texas Instruments patent family confirm that the approach enables NMOS and PMOS gate stacks to be independently engineered with separate metal layers.

Work function differentiation in the replacement gate flow is achieved by depositing different metal layers selectively into NMOS and PMOS gate recesses. A 2022 GlobalFoundries patent describes a sophisticated multi-step fill process: a conformal sacrificial metal cap material (SMCM) layer is formed above a high-k gate insulation layer within both NMOS and PMOS replacement gate cavities; the SMCM is selectively removed from one cavity while remaining in the other; then a first conformal metal-containing material layer is deposited; that layer is removed from one cavity; and finally a second conformal metal layer fills both cavities — yielding independently programmed work functions for each transistor type. A 2015 GlobalFoundries patent extends this by driving lanthanide-based material into the high-k layer via thermal processing within the gate recesses, further tuning threshold voltages without exposing the stack to front-end high temperatures.

EOT scaling in the replacement gate flow remains a challenge even with the thermal freedom it provides. IBM Thomas J. Watson Research Center research from 2012 shows that La-based higher-k materials (k > 20) can achieve EOT as low as 0.5–0.8 nm, but with effective work functions suitable primarily for NMOS. Remote interfacial layer (IL) scavenging — reducing the SiO₂ IL thickness by chemical or thermal means after gate stack deposition — can push EOT below 0.5 nm, but risks loss of effective work function (EWF) control and severe mobility degradation if the IL is eliminated entirely. These EOT–mobility–EWF trade-offs must be resolved within the replacement gate framework for each successive technology node, as documented by IBM researchers.

Hybrid High-k-First/High-k-Last: The Leading Industrial Solution

Recognizing that neither purely gate-first nor purely gate-last approaches simultaneously optimize NMOS and PMOS device characteristics, Texas Instruments developed and patented a hybrid integration scheme spanning multiple active jurisdictions — US (2016, 2018), EP (2016, 2025), JP (2017), WO (2015), and CA (2015) — making it the most extensively protected HKMG integration architecture in the dataset.

The invention provides “a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.” The NMOS device is processed gate-first, benefiting from the superior quality of a thermally grown SiO₂ interfacial layer, which improves channel mobility and interface trap density. The PMOS device is processed gate-last, with the high-k dielectric deposited into the replacement gate recess atop a chemically grown interfacial dielectric.

TiN work function engineering within this hybrid framework is described in a Texas Instruments EP patent active through 2026: a thick TiN metal gate with work function greater than 4.85 eV is formed for PMOS replacement gate transistors, and a thin TiN metal gate with work function less than 4.25 eV is formed for NMOS replacement gate transistors, while a gate-first TiN option is also provided where both NMOS and PMOS receive the same TiN deposition differentiated by thickness or subsequent doping. This vertical coverage — from process architecture down to individual metal layer specifications — reflects the breadth of Texas Instruments’ intellectual property position in HKMG integration.

The 2018 review of work function setting in high-k metal gate devices, published in academic literature and drawing on data from multiple technology nodes, confirms that both gate-first and gate-last schemes have been implemented in high-volume production, and that the dominant direction at leading-edge nodes (sub-22 nm) has moved toward gate-last or hybrid architectures because of their superior work function control. According to IEEE publications tracking process node evolution, this trend has continued as FinFET and gate-all-around architectures adopted replacement gate flows as a baseline.

Gate-Stack Material Engineering at Advanced Nodes

Beyond the gate-first vs. gate-last process topology, advanced nodes require careful gate-stack material engineering to maximize the Ion/Ioff ratio and suppress leakage — and the choices made within an established integration scheme can deliver measurable performance gains without requiring a full process node change.

Samsung Electronics’ 2021 study on 28 nm low-power HK/MG devices provides a direct experimental demonstration: by replacing HfSiON with HfSiO thin films and engineering the TiN layer thickness within the gate stack, the electrical oxide thickness was reduced by 3.1% for NFET devices, improving the Ion/Ioff ratio for a given Ion target while appropriately suppressing gate leakage. This result shows that sub-layer composition engineering — the choice between HfSiO and HfSiON — yields quantifiable performance improvements even within an established gate-last process at a mature node.

An important practical constraint emerges when integrating embedded non-volatile memory alongside HKMG logic transistors. A Cypress Semiconductor JP patent from 2019 highlights that at 28 nm and beyond, integrating embedded SONOS-type NVM alongside HKMG logic requires significant additions to the mask set and process steps, because the NVM gate stack must be formed before or after the HKMG stack without disrupting either. This integration complexity is typically easier to manage in gate-last flows, where the late-stage gate fill step can be tailored per device type — a practical consideration that has influenced the adoption of replacement gate flows at foundries offering embedded NVM options.

At the most aggressive EOT targets, the replacement gate’s thermal freedom does not eliminate all scaling trade-offs. As documented by researchers at IBM, zero-IL conditions achieved through metal gate capping layers (e.g., TiN atop HfO₂) introduce severe EWF instability and channel mobility degradation, underscoring that EOT scaling below 0.5 nm remains a multi-variable optimization problem even within the replacement gate framework. These findings are consistent with the broader scaling roadmaps tracked by ITRS and successor organizations, which identify gate stack scaling as a persistent challenge at each successive node.

Head-to-Head: Gate-First vs. Gate-Last at a Glance

The fundamental trade-off between gate-first and gate-last integration is between interface dielectric quality — which favors gate-first for NMOS — and work function and EOT controllability, which favors gate-last for PMOS and aggressive scaling nodes. The table below consolidates the key technical attributes drawn from the patent and literature dataset.

The patent landscape reflects clear organizational specialization: Texas Instruments owns the hybrid architecture space; GlobalFoundries drives multi-work-function replacement gate process innovations; the Institute of Microelectronics at the Chinese Academy of Sciences anchors gate-first dual-metal methodology; and IBM and Samsung contribute foundational literature on EOT limits and applied process engineering. Together, these assignees have defined the technical boundaries within which every leading-edge CMOS foundry now operates.