HCI: Lateral-field degradation and the self-heating inversion

Hot carrier injection is driven by the lateral electric field in the transistor channel. When carriers acquire sufficient kinetic energy from this field, they dissociate Si-H or Si-O bonds at the gate dielectric interface or within the oxide bulk, generating interface traps and oxide traps that degrade threshold voltage (V_th), saturation drain current (I_Dsat), and carrier mobility. Research from the ZJU-UIUC Institute at Zhejiang University (2022) confirms that HCI generates these traps primarily by dissociating Si-H or Si-O bonds, directly affecting device performance parameters including threshold voltage and saturation current.

The microscopic process underpinning HCI involves both single-carrier and multiple-carrier bond dissociation mechanisms. The balance between these two pathways depends on the carrier energy distribution function, which must be computed by solving the Boltzmann transport equation — a physics-based approach developed by TU Wien (2020) in their modeling framework for nanowire FETs. That work identified a threefold effect of self-heating on HCI: it significantly distorts the carrier distribution function, decreases the vibrational lifetime of the Si-H bond (thereby suppressing the multiple-carrier mechanism), and increases the rate of thermal bond breakage.

At 3nm, where nanowire or nanosheet gate-all-around (GAA) transistors have extremely limited thermal dissipation pathways, this self-heating effect (SHE) and HCI coupling becomes unavoidable. The increasing heat generation per unit volume at high integration densities creates a severe SHE in nanoscale FETs — and unlike in long-channel conventional MOSFETs where high temperature relaxes carrier energy, high temperature in nanoscale FETs actually deteriorates HCI reliability.

Work from the Institute of Microelectronics at Peking University (2021) advances a unified compact model combining contributions from both interface and oxide traps that accurately predicts hot carrier degradation across the full V_gs/V_ds bias space in FinFET technology. Two distinct types of oxide traps contributing to HCI are experimentally identified, and the temperature dependence of each trap type is characterized in detail. This trap-based physical picture has replaced the older empirical substrate current model as the standard approach for 3nm-relevant HCI modeling.

For lifetime prediction under practical operating conditions at 3nm — where supply voltage varies and stress conditions are non-static — the equivalent degradation method has been applied by Moyuan Computational Science (Nanjing) Co., Ltd. (2024), which proposes accumulating degradation over time under changing stress voltage and temperature parameters to arrive at accurate HCI lifetime estimates. Zhejiang University’s pending framework (2026) further reduces the test burden by requiring only V_th and I_Dsat degradation measurements to extract interface trap density (ΔNIT) and oxide trap density (ΔNOT), then predicts full I-V characteristic degradation using a compact model.

BTI: Vertical-field trapping, recovery, and stochastic single-trap events

Bias temperature instability operates through a thermally activated trapping and interface-state generation process driven by the vertical electric field across the gate dielectric, combined with elevated temperature. In p-MOSFETs under negative gate bias (NBTI), this combination creates a positive threshold voltage shift (|ΔV_th| increase), a reduction in drain current and transconductance, and an increase in subthreshold slope. For n-MOSFETs, positive bias temperature instability (PBTI) has historically been considered secondary, but becomes significant in the high-k dielectric stacks now universally employed at 3nm.

A critical differentiator of BTI from HCI at 3nm is its recovery behavior. When the stress bias is removed, a substantial fraction of the threshold voltage shift recovers on a timescale similar to the original stress. This recovery originates from the discharge of oxide traps that were charged during stress. Research published in 2016 on mitigating NBTI and PBTI degradation highlights that BTI recovery makes modeling particularly challenging because measurement delay — even microseconds — can cause significant underestimation of the true degradation magnitude.

PBTI in n-MOSFETs in SiON stacks involves contributions from both electron and hole traps. TU Wien’s (2020) time-dependent defect spectroscopy (TDDS) at the single-defect level reveals that hole traps account for approximately 20% of the total threshold voltage drift even in nominally n-channel devices — a finding that complicates the standard assumption that PBTI is a purely electron-trapping phenomenon, and that has direct consequences for reliability budgeting in 3nm n-type GAA transistors.

“Hole traps account for approximately 20% of the total threshold voltage drift even in nominally n-channel devices under PBTI stress — a finding revealed by time-dependent defect spectroscopy at the single-defect level.”

TSMC’s patent portfolio on NBTI prediction methodology — including its 2007 Method of NBTI Prediction and subsequent apparatus filings in 2011 and 2012 — establishes that NBTI lifetime can be estimated by measuring gate leakage current under a single stress bias sufficient to cause 10% drive current degradation, exploiting the correlation between gate leakage and trap density. At 3nm, where gate oxide leakage is already enormous by design, adapting such correlation-based methods requires recalibration against high-k dielectric physics, making these foundational patents engineering references rather than direct application toolkits.

The stochastic nature of BTI becomes increasingly dominant as device area shrinks. Peking University’s patents on predicting NBTI dynamic fluctuation at device end-of-life (2014, extended 2017) address the fact that at nanoscale dimensions, the number of traps in the gate dielectric is so small that individual trap capture and emission events produce discrete, stochastic threshold voltage fluctuations — effectively random telegraph noise (RTN). Device-to-device variation (DDV) and cycle-to-cycle variation (CCV) in BTI degradation must both be modeled, and this stochastic behavior becomes the dominant circuit reliability concern in SRAM bit cells and analog mirror circuits at 3nm node dimensions.

Research from the China Electronic Product Reliability and Environmental Testing Research Institute (2020) on partially depleted SOI pMOSFETs demonstrates that both oxide trap charge and interface traps lead to transfer characteristic degradation after NBTI stress, while near-interfacial traps specifically result in increases in low-frequency noise (LFN). This two-component picture is particularly relevant at 3nm, where the extremely thin equivalent oxide thickness (EOT) in high-k/metal-gate stacks maximizes both vertical field stress and the density of pre-existing border traps available for fast charge trapping.

Head-to-head: Six critical differences at 3nm

Six properties distinguish HCI from BTI in ways that directly determine how each mechanism must be characterized, modeled, and mitigated in 3nm process qualification and circuit design. The table below summarises these distinctions; the paragraphs that follow provide the physical basis for each.

Stress condition sensitivity and supply voltage compression

HCI is most severe under high drain bias at intermediate gate voltage — the bias condition that maximises substrate current and carrier impact ionisation rates. BTI is worst under high gate-to-source bias with low drain bias. At 3nm, the compressed supply voltage (typically approximately 0.75V for logic) reduces both fields, but the proportional severity of BTI tends to increase relative to HCI compared to older nodes: reducing supply voltage suppresses the peak lateral field more than the vertical overdrive stress. LSI Corporation’s 2014 patent on HCI reliability checks based on BTI-HCI interaction encodes this distinction operationally by measuring HCI-exclusive I_Dsat degradation through subtracting the BTI component from the combined stress measurement.

Spatial asymmetry as a diagnostic tool

HCI trap generation is most concentrated at the drain-side of the channel, where the lateral electric field is highest and impact ionisation peaks. This asymmetric damage is a diagnostic signature: the resulting threshold voltage shift under HCI stress is strongly dependent on source-drain bias direction, a property absent in BTI, which is symmetric along the channel. Peking University’s 2014 patent on separating reliability effects in SOI PMOSFETs exploits precisely this directionality, comparing threshold voltage shifts under simultaneous gate+drain stress versus gate-only stress to cleanly separate HCI and NBTI contributions. At 3nm, with gate lengths below 12nm, the drain-side damage region becomes a significant fraction of the total channel length, making this spatial distinction less clear than at 130nm.

Recovery, reversibility, and AC stress implications

HCI-induced damage, particularly interface trap generation from Si-H bond breakage, is largely permanent under normal operating temperatures. Oxide traps generated by HCI can partially anneal, but the irreversible component is dominant at device lifetime timescales. BTI, by contrast, exhibits substantial recovery upon removal of the stress bias. This recovery asymmetry is the primary reason why AC stress conditions (switching waveforms) are far more representative of BTI lifetime than DC stress, while HCI lifetime predictions are more robust to AC vs. DC differences. Research from Daegu University (2015) on on-chip delay degradation measurement for aging compensation identifies the need to monitor both NBTI and HCI in integrated aging compensation circuits at advanced nodes, precisely because the two mechanisms respond differently to dynamic operating conditions.

Why HCI and BTI cannot be modelled independently at 3nm

At 3nm, HCI and BTI are no longer independent degradation mechanisms. Under simultaneous high-V_gs and high-V_ds stress — the condition typical of switching transistors — both mechanisms are activated concurrently, and the self-heating induced by high current density couples them through the device temperature. Accurate 3nm reliability modelling therefore requires a fully coupled HCI-BTI-SHE treatment.

The separation of HCI and BTI in measurements requires specific bias configurations that exploit their physical differences. Peking University’s SOI PMOSFET separation patents use the directional asymmetry of HCI (drain-side damage) versus the symmetric nature of BTI. LSI Corporation’s simulation-based correction approach subtracts the BTI component (measured as a function of gate voltage alone) from the combined stress measurement to isolate HCI-exclusive I_Dsat degradation, then constructs an artificial HCI lifetime equation decoupled from BTI contributions. These methodologies are foundational for extracting accurate, mechanism-specific degradation data from 3nm test structures.

Compact modeling for 3nm must capture both ΔV_th and ΔI_Dsat simultaneously. The framework from Zhejiang University (2026 pending) demonstrates that extracting interface trap density and oxide trap density from these two measurements enables full I-V characteristic prediction, addressing the dual-mechanism nature of degradation at advanced nodes. This approach also significantly reduces the test burden for 3nm process qualification compared to traditional multi-bias stress matrices. According to IEEE reliability standards and reporting from WIPO‘s technology trend analyses, the shift toward physics-based coupled models represents the frontier of semiconductor reliability methodology as documented in the PatSnap Insights knowledge base.

Patent landscape and key research contributors

The approximately 50 patent filings and peer-reviewed literature entries in this dataset reveal a clear progression from single-mechanism, empirical lifetime models toward physics-based, multi-mechanism, coupled frameworks — driven by the recognition that decoupled HCI and BTI models are insufficient for 3nm technology characterisation. Five organisations define the frontier.

TSMC holds the most concentrated patent portfolio on BTI prediction methodology in this dataset, with multiple US patents on NBTI lifetime prediction using gate leakage current correlation. This portfolio reflects TSMC’s process engineering need for efficient in-line reliability screening across successive technology generations. Organisations such as TSMC and standards bodies including JEDEC continue to shape how reliability qualification standards evolve for sub-5nm nodes.

Peking University is the most prolific academic assignee on mechanism separation and stochastic lifetime modeling, with patents on separating HCI and NBTI threshold voltage shifts in SOI PMOSFETs (2013, 2014) and multiple patents on NBTI stochastic fluctuation prediction (2016, 2017). TU Wien is the leading academic group on physics-based HCI and BTI modeling in FinFET and nanowire architectures. ZJU-UIUC Institute and Dalian University of Technology contribute the most recent (2022) comprehensive survey and TCAD analysis of HCI in nanoscale FETs with self-heating coupling, representing the frontier of understanding relevant to 3nm. LSI Corporation and IBM hold key US patents on integrated EDA methodologies: LSI on the BTI-HCI interaction correction in simulation (2014) and IBM on in-line NBTI monitoring via hole injection (2003). The PatSnap IP intelligence platform provides full access to this assignee landscape and citation networks across all major semiconductor reliability patent families.

A clear trend across the dataset is the progression from single-mechanism, empirical lifetime models (early TSMC, Mitsubishi, AMD patents) toward physics-based, multi-mechanism, coupled frameworks (TU Wien, Peking University, ZJU-UIUC, 2020–2026), driven by the recognition that decoupled HCI and BTI models are insufficient for 3nm technology characterisation. This trend aligns with broader observations from OECD technology forecasting on semiconductor R&D investment concentration in advanced process nodes.