Why DC Fault Protection Is a Fundamentally Different Problem

DC fault currents do not cross zero — and that single physical fact reshapes every aspect of circuit breaker design. In AC systems, mechanical contacts can simply wait for the natural current zero that arrives 100 times per second; the arc extinguishes on its own. In DC systems, no such zero exists, which means a solid-state circuit breaker must actively force the current to zero through switching action, and must do so fast enough — typically within microseconds — to prevent catastrophic damage to the semiconductor switches and downstream equipment.

The rapid rise of DC microgrids — driven by the proliferation of photovoltaic generation, battery storage, EV charging infrastructure, and data-centre power distribution — has intensified demand for protection devices that can operate at voltages from 380 V (low-voltage DC bus) through to several kilovolts in medium-voltage applications. According to IEEE standards bodies, the absence of standardised DC protection frameworks has historically slowed adoption, making the engineering choices around SSCB design even more consequential for system architects.

The consequences of a slow or failed interruption in a DC microgrid are severe: without a current zero to exploit, an uncleared fault can drive current to levels that destroy power converters, damage battery systems, and compromise bus integrity across the entire microgrid. This places the SSCB at the centre of system reliability — not merely as a protective element, but as a critical enabler of the architecture itself.

Semiconductor Device Selection: Silicon vs. Wide-Bandgap Materials

The choice of switching device is the single most consequential design decision in a high-voltage SSCB. Silicon IGBTs and MOSFETs have historically dominated power switching applications, but wide-bandgap (WBG) semiconductors — principally silicon carbide (SiC) and gallium nitride (GaN) — are increasingly displacing silicon in high-voltage SSCB designs due to their superior combination of breakdown voltage, switching speed, and thermal tolerance.

SiC MOSFETs are particularly well-suited to high-voltage DC breaker applications. Their breakdown field — roughly ten times that of silicon — allows a given voltage rating to be achieved with a much thinner drift layer, which directly reduces on-state resistance and conduction losses. For a DC microgrid SSCB that must carry rated current continuously while remaining ready to interrupt a fault, minimising conduction loss is as important as achieving fast switching, because thermal dissipation in the semiconductor directly constrains the current-carrying capacity of the device.

GaN devices, by contrast, excel at high-frequency switching and have a natural advantage in lateral device geometries suited to lower-voltage DC bus applications (typically below 650 V). For higher-voltage medium-voltage DC (MVDC) applications above 1 kV, SiC currently holds a practical advantage due to the maturity of vertical SiC MOSFET and SiC JFET device families. Research published by IEEE confirms that SiC-based breakers have demonstrated interruption times well below 10 microseconds in experimental validation — a performance level unachievable with silicon IGBTs at comparable voltage ratings.

“The choice between SiC and GaN is not merely a component selection — it defines the voltage ceiling, the loss budget, and the thermal architecture of the entire SSCB system.”

SSCB Topologies and Their Trade-offs

Three principal circuit topologies dominate the SSCB design space for DC microgrid protection, each representing a different balance between interruption speed, conduction loss, and system complexity. Understanding these trade-offs is essential before selecting a protection architecture.

1. All-Solid-State Topology

The all-solid-state SSCB replaces all mechanical components with semiconductor switches arranged in a bidirectional configuration. This topology achieves the fastest interruption times — sub-microsecond in optimised designs — because there is no mechanical travel time. The penalty is continuous conduction loss: the semiconductor switches carry rated current at all times, and even low on-state resistance devices dissipate meaningful power at high current levels. Thermal management is therefore a primary design constraint, and heatsinking or active cooling is typically required for ratings above a few hundred amperes.

2. Hybrid Topology

The hybrid SSCB combines a normally-closed mechanical bypass (a fast vacuum switch or a low-resistance relay) with a solid-state switching element in series. Under normal operating conditions, current flows through the low-resistance mechanical path, eliminating continuous semiconductor conduction losses. When a fault is detected, the mechanical bypass opens and current commutates to the solid-state element, which then interrupts the fault. This topology achieves near-zero conduction losses at the cost of slightly slower response — typically in the range of hundreds of microseconds — due to the finite opening time of the mechanical element.

3. Resonant Current-Injection Topology

The resonant topology addresses the absence of a natural current zero in DC systems by actively creating one. A resonant LC circuit, pre-charged or triggered at the moment of fault detection, injects an oscillating counter-current into the main circuit. When the injected current equals the fault current, the net current through the interrupting device passes through zero, enabling arc-free interruption. This approach can be implemented with lower-rated semiconductor switches than a direct-interruption design, but the auxiliary resonant circuitry adds component count, volume, and design complexity.

Energy Absorption and Overvoltage Clamping

When a high-voltage SSCB interrupts a DC fault, the inductive energy stored in the circuit — proportional to ½LI² — must be dissipated somewhere. If it is not managed, the voltage across the opening switch will spike to levels that exceed the semiconductor’s rated breakdown voltage, destroying the device in the very act of protecting the system.

Three energy absorption strategies are in common use. Passive clamping using transient voltage suppression (TVS) diodes or metal-oxide varistors (MOVs) is the simplest approach: these devices clamp the voltage across the switch to a defined level and absorb the inductive energy as heat. Their limitations are energy capacity and response speed — MOVs in particular have a finite energy absorption rating, and repeated fault interruptions can degrade them. Active gate-drive clamping modulates the gate signal to control the rate of current fall (dI/dt), reducing the peak voltage overshoot at the cost of a longer interruption transient. Regenerative snubber circuits capture the inductive energy and return it to the DC bus rather than dissipating it as heat — an approach that improves system efficiency but adds significant circuit complexity.

Thermal management is inseparable from energy absorption design. The power dissipated in the clamping elements during a fault event is concentrated into a very short time window, creating a high peak power density that can exceed the steady-state thermal rating of the component by orders of magnitude. Junction-to-case thermal impedance, heatsink design, and — in high-cycle applications — the thermal fatigue characteristics of the semiconductor packaging must all be considered as part of the SSCB system design. Standards bodies including IEC and IEEE are actively developing test methodologies to characterise SSCB thermal performance under repeated fault cycling conditions.

Where to Find Authoritative SSCB Patent and Research Data

Engineers and IP professionals seeking to understand the current state of SSCB innovation for DC microgrid protection have access to several high-quality primary sources. Knowing which databases to query — and which classification codes to use — significantly accelerates landscape analysis.

Patent Databases and IPC Classification Codes

The three most relevant International Patent Classification (IPC) codes for SSCB searches are H02H 3/02 (emergency protective circuit arrangements responsive to excess current), H01H 33/59 (circuit breaker contacts and arc-extinguishing arrangements), and H02J 1/00 (circuit arrangements for DC power supply). Searches across WIPO‘s PatentScope, the USPTO full-text database, and the EPO’s Espacenet using these codes — combined with keyword terms such as “solid-state circuit breaker,” “DC microgrid protection,” “fault current interruption,” and “wide-bandgap semiconductor breaker” — will retrieve the most relevant patent families.

Technical Literature

IEEE Xplore is the primary repository for peer-reviewed SSCB research, with relevant publications appearing in IEEE Transactions on Power Electronics, IEEE Transactions on Industrial Electronics, and conference proceedings from ECCE, APEC, and IECON. Search terms including “SiC SSCB,” “GaN circuit breaker,” “DC fault isolation,” and “hybrid DC breaker” will surface the most cited work in this area. For materials-level research on wide-bandgap device reliability, journals published by Nature and its electronics-focused titles provide foundational semiconductor physics data.

Using PatSnap Eureka for Rapid Landscape Analysis

PatSnap Eureka’s AI-native search platform enables engineers and IP teams to run natural-language queries across global patent and literature databases simultaneously, map technology clusters, identify key assignees, and track filing trends — capabilities that compress weeks of manual database searching into hours. For a domain as technically specific as high-voltage SSCB design, where relevant patents may be classified across multiple IPC codes and claim language varies significantly between jurisdictions, AI-assisted search substantially reduces the risk of missing key prior art.