The Core Mechanism: How Hybrid Bonding Works

Hybrid bonding is a direct bonding process that simultaneously forms two bonded interfaces — metallic (copper-to-copper) and dielectric (oxide-to-oxide or polymer-to-polymer) — without any solder bumps, underfill, or intermediate adhesive materials. This dual-interface formation is what distinguishes it from every prior interconnect technology and is the reason it enables connection pitches below 10 μm, a threshold that conventional flip-chip bumping cannot reach.

The process unfolds in two distinct phases. First, at room temperature, the two wafers or dies — each comprising a dielectric layer (typically SiO₂, SiCN, or an organic polymer) with metallic copper pads recessed slightly below the dielectric surface — are brought into contact after chemical-mechanical planarization (CMP) and plasma surface activation. The dielectric surfaces bond through van der Waals forces and covalent Si-O-Si bridges at the activated interface. Adeia Semiconductor Bonding Technologies’ 2023 disclosure specifically describes exposing the dielectric bonding surface to water vapor plasma products prior to contact to maximize covalent bond formation.

Second, during thermal anneal — typically between 150°C and 400°C — the copper pads expand due to coefficient of thermal expansion (CTE) mismatch, filling the recessed gap and forming grain-grain contact. Grain boundary diffusion and surface diffusion then create a fully dense, void-free metallic joint. Researchers at National Yang Ming Chiao Tung University confirmed in 2023 that copper oxidation is a central challenge: the thermal budget required to drive copper diffusion simultaneously risks wafer warpage and back-end-of-line process degradation.

The precise geometry required for this dual-interface bond is tightly controlled. Huawei Technologies’ 2022 patent specifies that the first metal surface must be slightly higher than the first insulation dielectric surface, creating a designed gap area that allows both longitudinal and transverse deformation of copper upon contact and annealing, while simultaneously permitting dielectric-to-dielectric closure. This nano-scale geometry management is what makes the dual-interface bond achievable in a single thermal step.

“A (111)-oriented Cu microstructure substantially outperforms grain boundary diffusion below 250°C — making crystallographic orientation the key lever for low-temperature hybrid bonding.”

The kinetics of copper grain closure were quantitatively modeled by Chen et al. at National Yang Ming Chiao Tung University in a 2021 paper with 82 citations. Their surface creep model shows that a pressure gradient drives atomic layers to fill voids at the bonding interface, with effective diffusivity (D_eff) dominated by either surface diffusion or grain boundary diffusion depending on crystal orientation. A (111)-oriented Cu microstructure was identified as the most promising path to achieving bonding below 250°C, since the (111) surface diffusivity substantially outperforms grain boundary diffusion at those temperatures.

Surface Preparation and Process Integration: The Yield-Critical Steps

The reliability of hybrid bonding is entirely dependent on the quality of bonding surfaces — planarity, cleanliness, and chemical state are the primary yield levers, and the patent literature addresses each extensively.

Dual-Step Plasma Activation

Yangtze Memory Technologies (YMTC) disclosed a two-step plasma activation process for wafer bonding in a 2019/2020 patent. The method first applies an oxygen or inert-gas plasma to clean and oxidize the surface, then applies a water molecule-based plasma to introduce hydroxyl (-OH) groups that drive covalent bonding upon contact. This dual-plasma approach maximizes bond strength at temperatures compatible with 3D NAND flash integration, and according to WIPO records represents an important contribution to the Chinese domestic 3D NAND manufacturing capability.

Probe Pad Damage Mitigation

A persistent manufacturing challenge is that electrical testing (probing) of wafers before bonding damages the copper pad surfaces, degrading the flat bonding interface needed for direct bonding. Adeia Semiconductor Bonding Technologies holds a broad patent family addressing this: US11355404B2 (50 citations) and its continuation US20200335408A1 (139 citations) disclose building probe pads on sub-surface metallization layers, then applying damascene-processed dielectric and copper layers over the disrupted surfaces to reconstitute a bonding-ready planar interface without adding mask layers.

Substrate Cleaning and In-Situ Metrology

Applied Materials addresses pre-bond surface contamination in a 2024 patent disclosing a brush-box cleaning module integrated into the bonding platform. The module removes both chemical residues and mechanical particles from backgrinding and dicing tape — the primary contamination sources in die-level stacking — without causing scratches, watermarks, or surface roughness that would compromise bonding yield.

Tokyo Electron Limited has advanced real-time process control with X-ray integrated metrology in a 2024 patent, where an X-ray source and detector are co-located with the bonder head to measure relative misalignment of the two bonded structures during the bonding event itself. This enables closed-loop alignment correction in real time for sub-micron overlay targets — a critical capability as pitch shrinks toward and below 1 μm. Standards bodies such as IEEE have identified sub-micron overlay control as one of the primary technical challenges for next-generation 3D integration.

Application Domains: From 3D NAND to Panel-Level Packaging

Hybrid bonding has moved from a laboratory technique to a high-volume manufacturing process across three distinct application domains — each with different pitch requirements, substrate formats, and stacking geometries.

Wafer-to-Wafer and Die-to-Wafer Stacking

The earliest and highest-volume application of hybrid bonding is wafer-to-wafer (W2W) stacking for 3D NAND flash — pioneered by YMTC’s Xtacking architecture — and 3D image sensors, pioneered by Sony. TSMC’s foundational 2015 patent (US9048283B2, 27 citations) established the multi-chamber system architecture: a single-platform system with sub-chambers dedicated to protection layer removal, surface activation, and wafer alignment and bonding. This single-platform process integration architecture was subsequently adopted by later equipment generations.

Die-to-wafer (D2W) hybrid bonding is addressed by Applied Materials in a 2024 patent disclosing a method where multiple dies are hybrid bonded to a substrate, then selectively thinned via silicon etch, passivated, and the inter-die gaps filled with dielectric — enabling 3D stacking of heterogeneous dies without requiring a monolithic wafer. This approach directly addresses the manufacturing requirements of DRAM and high-bandwidth memory (HBM) production.

Advanced Panel-Level Packaging

Applied Materials extends hybrid bonding beyond circular wafers to rectangular substrate panels in a 2025 patent (JP2025523165A), targeting a heterogeneous integration architecture where semiconductor structures with exposed conductive connections at pitches below 10 μm are bonded to large-format rectangular panel substrates. Panel-level processing offers significant cost reduction potential for chiplet-based designs by increasing the number of dies processed per production run. The Semiconductor Industry Association has identified chiplet integration as a primary pathway for continuing performance scaling beyond traditional node shrinks.

Intel’s Ultrathin Bridge Architecture

Intel Corporation disclosed a hybrid bonding application for die-to-die connectivity using an ultrathin bridge in a 2021 patent. The bridge comprises a hybrid layer with conductive pads, surface finishing, and dielectric, and is directly coupled to multiple dies with the hybrid layer top surface in direct contact with die bottom surfaces. Bonding employs temperature, pressure, and reducing atmosphere — consistent with the standard hybrid bonding anneal sequence — and targets ultrafine pitch die-to-die interconnects for multi-chiplet processor packages.

Thermal cycling reliability of copper-copper hybrid bumps was studied by National Yang Ming Chiao Tung University (2021, 36 citations), confirming that post-annealing bonding eliminates the bonding interface grain boundary — the primary site for fatigue crack initiation under thermal cycling — validating long-term reliability for automotive and high-performance computing applications.

Key Patent Holders and the Innovation Landscape

The hybrid bonding patent landscape is concentrated among a small number of dominant assignees, each with distinct technical focus areas — from foundational bonding structures to process equipment and yield-enabling methodologies.

Adeia Semiconductor Bonding Technologies (formerly Invensas/Ziptronix) is the most prolific assignee in the direct bonding space by citation impact. Beyond probe pad mitigation, Adeia is pushing next-generation architectures with flexible hybrid bonding layers on organic dielectrics (2026 publication), targeting bendable interconnect structures. Their water vapor plasma activation disclosure (2024) is a primary process route for room-temperature dielectric pre-bonding.

Applied Materials is the leading equipment company in hybrid bonding process integration, covering the full sequence from substrate cleaning and surface activation to multi-layer die stacking and panel-level bonding. Their 2024 patents on D2W stacking and substrate cleaning reflect DRAM and HBM manufacturing requirements, while their 2025 panel-level patent signals the next cost-reduction frontier.

TSMC holds foundational wafer-level hybrid bonding system IP and is the primary high-volume manufacturer of SoIC (System on Integrated Chips) products using W2W and D2W hybrid bonding. A 2023 TSMC patent discloses dielectric fill materials — spin-on-glass and polymer — between side-by-side dies in a stacked structure, a key detail for chiplet-scale integration. According to OECD technology reports, advanced packaging is now a primary competitive differentiator in global semiconductor supply chains.

Huawei Technologies has contributed significant innovation in the geometric design of copper-dielectric co-planarity requirements. Their granted patent US11756922B2 (2023) is a key reference for the structural engineering of the hybrid bonding interface. Tokyo Electron Limited leads in in-situ process metrology, with X-ray-based overlay measurement integrated into the bonding head — positioning them as a critical enabling equipment vendor for sub-micron pitch quality control. YMTC originated the two-step plasma activation process, reflecting China’s investment in domestic 3D NAND manufacturing.

Frontier Variants: Polymer Dielectrics, Low-Temperature Bonding, and What Comes Next

Silicon dioxide (SiO₂) is no longer the only viable dielectric for hybrid bonding — polymer-based variants and further thermal budget reductions are the two most active research frontiers, each driven by specific application requirements.

Polymer-Based Hybrid Bonding

SanDisk Technologies filed a 2024/2026 patent disclosing a 3D NAND architecture where copper bonding pads are embedded within a polymer dielectric layer rather than conventional SiO₂ or SiCN. Polymer dielectrics offer softer, more compliant bonding interfaces that may reduce stress-induced defects in tall memory stacks — a significant concern as 3D NAND layer counts continue to increase. This represents a frontier variant of hybrid bonding specifically optimized for ultra-high layer count 3D NAND manufacturing.

The academic foundation for this approach was established by researchers at the Chinese Academy of Sciences in a 2022 study demonstrating that oxygen plasma activation followed by wetting on polyimide surfaces achieves void-less dielectric bonding with a shear strength of 35.3 MPa at just 250°C in 2 minutes — a dramatic reduction in thermal budget compared to oxide-based bonding. Published findings in journals tracked by Nature have highlighted low-temperature bonding as a critical enabler for heterogeneous integration of temperature-sensitive compound semiconductor devices.

Adeia’s Flexible Hybrid Bonding Layers

Adeia Semiconductor Bonding Technologies’ 2026 publication on semiconductor elements with hybrid bonding layers on organic dielectrics targets bendable interconnect structures — a signal that hybrid bonding is beginning to extend beyond rigid silicon substrates into flexible electronics applications. This represents a significant expansion of the technology’s addressable market beyond traditional 3D IC packaging.

The 3D TSV Ecosystem

The broader 3D packaging ecosystem integrating hybrid bonding with through-silicon vias (TSVs) was reviewed by researchers at the University of Seoul and Ajou University in 2023 (47 citations), covering transient liquid phase bonding, copper pillars, composite hybrids, and bump-free bonding as they interact with TSV-based vertical connectivity. Hybrid bonding and TSV integration are increasingly complementary rather than competing technologies: TSVs provide vertical connectivity through the bulk silicon, while hybrid bonding provides the highest-density inter-die connections at the bonded interface.

“Post-annealing bonding eliminates the bonding interface grain boundary — the primary site for fatigue crack initiation under thermal cycling — validating the long-term reliability of the Cu-Cu joint for automotive and HPC applications.”