Why the FinFET Era Ended at Sub-5nm

Gate-all-around (GAA) transistors emerged as the mandatory successor to FinFET because conventional fin-shaped channels can no longer provide adequate electrostatic control at sub-5nm process nodes. In a FinFET, the gate wraps around three sides of a vertical silicon fin; in a GAA design, the gate fully encircles each horizontal channel layer — eliminating the leakage pathways that degrade FinFET performance at extreme scaling. Both Intel and TSMC have independently developed GAA implementations, but the architectural choices they have made diverge in ways that carry significant implications for chip designers, IP professionals, and foundry customers evaluating the 2nm landscape.

The patent and literature dataset underpinning this analysis spans approximately 60 sources across assignees including Intel Corporation, Taiwan Semiconductor Manufacturing Co., Qualcomm, GlobalFoundries, IMEC, and IBM. The dominant technical themes centre on nanosheet and nanoribbon channel architectures, complementary FET (CFET) stacking, hybrid SRAM cell designs, and the structural transition away from FinFET at sub-5nm nodes. Insights from bodies such as IEEE and consortium research from IMEC provide additional context for where the technology is heading.

The structural divergence between the two companies is not merely a matter of branding. Intel’s commercially marketed “RibbonFET” and TSMC’s “N2” process encode fundamentally different philosophies: Intel pursues aggressive vertical integration with fully 3D SRAM and an early CFET roadmap, while TSMC prioritises process integration continuity by retaining FinFET where it reduces manufacturing risk. Understanding these differences at the patent level is essential for anyone making platform or IP strategy decisions in the 2nm era.

Intel’s Nanoribbon Architecture: Width Tunability as a Differentiator

Intel’s RibbonFET is grounded in horizontally stacked semiconductor nanoribbon channels fully surrounded by a gate electrode, with the defining commercial advantage being the ability to tune drive strength continuously by varying ribbon width rather than discretely by adding fins. This width-tunability is a degree of freedom that conventional FinFET designs cannot offer, where drive strength is discretised by fin count.

Intel’s 2021 patent on 3D Nanoribbon-Based SRAM describes IC devices comprising stacked semiconductor nanoribbons suitable for forming NMOS and PMOS transistors within SRAM cells. The architecture supports multiple stacked nanoribbon layers to enable high-density 3D SRAM, demonstrating Intel’s integration philosophy of combining scaled transistor elements with vertical memory density improvements.

The 2023 patent on SRAM with Nanoribbon Width Modulation for Greater Read Stability takes this further, disclosing SRAM IC structures using pass-gate and pull-down transistors with different nanoribbon widths along a shared centreline. This width modulation technique — achievable through EUV lithography at 13.5 nm centre wavelength — reduces read instability without requiring additional read-assist circuitry. Research institutions including IMEC have noted that such geometric tuning within a single device is a key advantage of the ribbon form factor over nanowire-based GAA approaches.

Intel’s CFET-based register file work, disclosed in a 2024 patent, reveals the company’s roadmap: PMOS transistors arranged in stacked layers between metal routing levels, with vias connecting gate contacts to upper metal layers. This vertical integration of complementary transistor pairs is the architectural precursor to Intel’s next-generation CFET logic, underpinning the scaling strategy beyond RibbonFET at 2nm and toward the 18A and 14A nodes.

The 2024 patent on a Three-Transistor Embedded DRAM Gain Cell is particularly significant: CFET-based 3T gain cells provide 50% area scaling over conventional SRAM at equivalent storage node capacitance. Intel also holds patents on stacked transistor configurations mixing silicon PMOS and high-mobility thin-film NMOS, indicating exploration of material integration beyond pure silicon — a direction compatible with the RibbonFET platform.

“CFET-based 3T gain cells provide 50% area scaling over conventional SRAM at equivalent storage node capacitance — a metric that signals Intel’s intent to use RibbonFET as the foundation for a full CFET platform, not merely a transistor upgrade.”

TSMC’s Hybrid GAA Strategy at N2: Conservative by Design

TSMC’s GAA implementation at N2 is defined by a deliberate hybrid approach: GAA nanosheet channels are applied selectively to NMOS transistors while PMOS pull-up devices in SRAM cells retain FinFET geometry, reducing process integration risk at the cost of some ultimate scaling headroom. This is not a compromise born of technical inability — it is a strategy that maximises yield and design-rule compatibility with the existing FinFET ecosystem.

TSMC’s 2023 patent on Hybrid SRAM Design with Nano-Structures describes a semiconductor device where the NMOS region employs a first GAA device with a vertical stack of nanostructure channels, while the PMOS region employs either a FinFET or a second GAA device with a different number of nanostructure channels. A critical geometric constraint is stated explicitly: the maximum channel width of the nanostructure channels is not greater than the sum of fin width and fin spacing. This constraint preserves compatibility with the existing FinFET pitch grid, simplifying SRAM-logic co-integration across the die.

The area benefit of this selective GAA deployment is quantified in TSMC’s 2024 patent on Semiconductor Device and Method of Forming Semiconductor Device: replacing multiple FinFET fins in the NMOS region with a vertical stack of nanostructure channels (circumferentially surrounded by the gate electrode) allows TSMC to process higher drive current within the same footprint. The patent notes that “since multiple nanostructure channels each have their surface circumferentially surrounded by the gate electrode, and there are multiple nanostructure channels (e.g., three in the illustrated embodiment), the NMOS region can still handle at least as high a current as multiple fin structures.” Three stacked nanosheet channels in the NMOS region thus deliver FinFET-equivalent drive current in reduced area — without requiring a full redesign of the PMOS side.

TSMC’s earlier 2020 patent on Semiconductor Device and Circuit establishes the design methodology of matching logic device and SRAM device layouts through shared fin and gate pitch — a methodology that carries forward into the N2 process where SRAM and logic cells must co-exist on the same die with consistent pitch rules. This continuity of design methodology is a key competitive advantage for TSMC’s ecosystem of fabless customers, who can migrate existing IP blocks with lower re-design overhead.

Head-to-Head: Channel Geometry, SRAM Architecture, and CFET Readiness

Comparing Intel’s RibbonFET and TSMC’s N2 GAA across four dimensions — channel geometry, PMOS treatment, SRAM cell architecture, and CFET integration readiness — reveals that the two companies have made fundamentally different bets on where the primary scaling lever lies at 2nm.

Channel Geometry and Drive-Strength Tuning

Intel’s RibbonFET achieves drive-strength adjustment through continuous nanoribbon width modulation within a single transistor — a technique enabled by EUV lithography and confirmed in the 2023 SRAM with Nanoribbon Width Modulation patent. TSMC’s approach, by contrast, varies nanosheet channel count between devices: GlobalFoundries’ 2019 patent on GAA FET Integrated Circuit Structures with Different Drive Currents demonstrates a channel-count reduction method applicable to both vendors’ processes. These represent different manufacturing trade-offs: Intel’s approach requires tighter lithographic control per device; TSMC’s approach requires more complex multi-patterning or EUV steps to define different stack heights across the die.

PMOS Treatment

Intel’s stacked transistor patents indicate a strategy of applying GAA or stacked architectures to both device types, with potential use of alternative channel materials for NMOS. TSMC’s N2 process, as reflected in the 2024 German Hybrid SRAM Design patent, maintains FinFET for PMOS in SRAM pull-up transistors while deploying GAA only for NMOS pull-down and pass-gate transistors. This heterogeneous approach reduces process complexity but may limit the ultimate scaling benefit relative to an all-GAA cell.

SRAM Cell Architecture

Intel’s 2021 3D Nanoribbon-Based SRAM patent demonstrates vertically stacked nanoribbon layers hosting multiple SRAM cells per layer — a fully 3D memory architecture. TSMC’s SRAM co-optimisation prioritises 2D pitch alignment between logic and SRAM, with nanosheet channels replacing fins in the NMOS region to recover area. IMEC’s research — funded partly by TSMC’s supply chain — pushes further toward true 3D SRAM via a 2024 patent on High Performance and Low Power 3D SRAM Cell and Process Integration Flow, where pull-up and pull-down transistors occupy separate tiers with fin/nanosheet ratios adjusted between tiers (2:1 or 1:2 depending on which tier hosts the pass-gate). These IMEC developments have not yet appeared in production-ready N2 patent disclosures, indicating that TSMC’s ecosystem is developing 3D SRAM capabilities for a future node.

CFET Readiness

Intel’s patent portfolio shows more advanced CFET integration than TSMC’s published N2 patents. The 2024 N-P Balanced Multi-Port Register File with CFET and the 2024 3T Embedded DRAM Gain Cell disclosures both describe production-intent CFET geometries. Qualcomm’s 2025 CFET patent — targeting TSMC’s foundry process — reveals CFET structures with independently tuned nanosheet width-to-length ratios (W2/L2 ≠ W1/L1) across n-type and p-type stacks to equalise saturation currents, directly addressing PMOS and NMOS mobility imbalance. TSMC’s own published 2nm patents remain focused on nanosheet GAA rather than monolithic CFET, suggesting CFET is a post-N2 feature for TSMC.

The Broader Ecosystem: GlobalFoundries, IMEC, and Qualcomm

The 2nm GAA landscape extends well beyond Intel and TSMC. GlobalFoundries, IMEC, and Qualcomm each contribute IP that shapes how the technology evolves — and reveals unsolved problems that neither foundry has yet resolved in production-ready disclosures.

GlobalFoundries contributes to the GAA ecosystem through its 2019 patent on GAA FET Integrated Circuit Structures with Different Drive Currents, disclosing methods for forming GAA FETs with different numbers of nanosheet channels in the same chip — a drive-current tuning technique essential for mixed SRAM/logic designs at 2nm-class nodes. This channel-count reduction method is applicable to both Intel’s and TSMC’s process flows, making it a foundational cross-platform technique. According to standards bodies such as WIPO, GAA transistor patents have been among the fastest-growing categories in semiconductor IP filings over the past five years.

IMEC represents the academic and consortium research frontier. Its 2024 patent on High Performance and Low Power 3D SRAM Cell and Process Integration Flow discloses 3D SRAM cells where pull-up and pull-down transistors occupy separate tiers, with fin/nanosheet ratios adjusted between tiers (2:1 or 1:2 depending on which tier hosts the pass-gate). IMEC’s 2025 SRAM Device patent demonstrates that 8T dual-port CFET cells achieve a dual-port to single-port area ratio approaching parity — a key metric for AI and GPU SoC workloads where dual-port register files are critical. These IMEC developments are expected to influence future TSMC node designs, though they have not yet appeared in production-ready N2 patent disclosures.

Qualcomm holds significant CFET IP relevant to TSMC’s foundry process. The 2025 patent on Complementary FET with Balanced N and P Drive Currents discloses CFET structures with independently tuned nanosheet width-to-length ratios (W2/L2 ≠ W1/L1) across n-type and p-type stacks to equalise saturation currents. This directly addresses a key challenge in CFET-based 2nm design where PMOS and NMOS mobility imbalance must be corrected geometrically — confirming that drive current balancing between PMOS and NMOS remains an active, unsolved problem for CFET-based 2nm designs. Organisations tracking semiconductor standards such as NIST have highlighted PMOS/NMOS mobility asymmetry as one of the central barriers to monolithic CFET commercialisation.

The breadth of Intel’s filings — spanning nanoribbon-based SRAM (2021), nanoribbon width-modulation (2023), CFET-based register files (2024), 3T embedded DRAM gain cells (2024), and III-N transistor integration for SoC applications — signals a comprehensive platform strategy: RibbonFET is not a standalone transistor but the foundation for CFET stacking and heterogeneous integration. TSMC’s strategy is more conservative in transistor architecture and more aggressive in cell-level design integration, relying on its ecosystem of fabless customers and research partners to push the CFET frontier on its behalf. Both approaches reflect the reality that, as noted by researchers publishing through Nature Electronics, the transition to GAA and CFET is as much a manufacturing integration challenge as it is a device physics problem.