Why metal grain orientation shifts threshold voltage

Metal gate granularity (MGG) drives threshold voltage (Vt) variability because different crystal planes of work-function metals such as TiN, TaN, TiAl, and TiAlC expose different surface free energies to the gate dielectric, making the effective work function spatially non-uniform across the channel. Each grain subtends a fraction of the total gate area, and the ensemble of randomly oriented grains presents a varying electrostatic boundary condition to the channel beneath it. The statistical dispersion of threshold voltage that results — quantified by its standard deviation σVt — is what the community terms work function variation (WFV) or MGG-induced Vt variability.

Research from IIT Bombay (2018) established that MGG is “of paramount importance due to its large impact on VT variability” compared with other process-induced variabilities such as random dopant fluctuations (RDF) or line edge roughness (LER). The IIT Bombay team extended an earlier FinFET-based MGG analytical model to cylindrical nanowire FETs (NWFETs) by replacing the gate dielectric with an electrostatically equivalent silicon thickness via the long-cylinder approximation, enforcing periodic boundary conditions for metal grains in the azimuthal direction, and solving Poisson’s equation analytically in cylindrical coordinates with the gate boundary condition defined by the grain distribution. This work demonstrates that as device diameter shrinks — directly relevant to gate-all-around (GAA) nanosheet and nanowire transistors deployed at 5nm and below — the number of grains under the gate decreases and the central limit theorem no longer averages out grain-to-grain work function differences, causing σVt to rise sharply.

POSTECH’s 2022 experimental study corroborated the modelling picture using Pelgrom-plot analysis of silicon nanowire FETs with gate lengths of 15–22 nm and channel diameters of 7, 9, and 12 nm. Applying an error-propagation-law model to decompose σVt into contributions from WFV (grain-induced metal work function variation), channel dopant concentration (ΔNch), and diameter variation (ΔDNW), the authors found that WFV induced by metal grain orientation was the dominant variability contributor across all geometries studied. The σVt minimum occurred at the median channel diameter of 9 nm — a non-monotonic trend explained by the interplay between electrostatic gate coupling and grain boundary density. The Pelgrom plot exhibited a nonzero y-intercept attributable precisely to this grain-level mismatch, confirming that MGG cannot be modelled purely as an area-scaling phenomenon at these dimensions, in line with guidance from standards bodies such as IEEE on device variability characterisation.

The few-grain regime: when statistics break down below 5nm

Below 5nm, the gate volume of a transistor accommodates only a handful of metal grains — a condition the literature terms the “few-grain regime” — and the central limit theorem can no longer average out grain-to-grain work function differences, causing σVt to become non-Gaussian and invalidating the area-scaling assumptions that underpin conventional Pelgrom mismatch models. This transition is the core physical insight motivating the IIT Bombay cylindrical NWFET MGG model and its periodic boundary condition formulation, and it explains why academic models that were long predictive have now become directly industrially relevant as the industry moves to gate-all-around (GAA) nanosheet architectures at 2nm-class nodes.

“As gate dimensions contract below 5nm, the number of grains under the gate shrinks to single-digit figures, transforming MGG from a statistical nuisance into a device-limiting, quasi-deterministic mismatch source.”

The GAA architecture intensifies the MGG problem because metal must fill nanoscale slits between stacked nanosheets, constraining grain growth and increasing the likelihood of atypical crystallographic orientations. National Chiao Tung University (NCTU) demonstrated this in a 2019 study of TiN grain-induced WFV in a 10 nm gate-length GAA nanowire MOSFET, finding significant fluctuations in both DC threshold voltage and AC timing characteristics. The study further showed that varying the aspect ratio of the channel cross-section alters the effective grain ensemble geometry, thereby modulating σVt and propagating timing uncertainty into circuit-level power-delay products — a finding with direct implications for design-technology co-optimisation (DTCO) at advanced nodes, a methodology endorsed by bodies such as imec and tracked by WIPO in its annual technology trend reports.

In a conventional FinFET at 7nm, the gate wraps around a fin whose fin width and gate length together define a gate area that still accommodates multiple grains. In a 2nm-class nanosheet device, the gate metal fills a slit between stacked sheets only a few nanometers tall, drastically reducing the gate volume and with it the grain population. This geometric transition is not merely a quantitative change — it is a qualitative shift in the statistical character of MGG, from a well-behaved Gaussian distribution amenable to Pelgrom-plot characterisation to a sparse, discrete distribution whose tails are determined by single-grain events. The University of Santiago de Compostela’s 2021 study reinforced this by evaluating MGG as one of four variability sources (alongside LER, GER, and RDD) in GAA NW FETs and finding that the extraction method itself introduces systematic offsets in σVt estimation — a practical challenge for process monitoring and statistical design at 5nm and below.

Gate-stack engineering strategies to suppress MGG-induced variability

Process engineers have pursued multiple strategies to reduce grain orientation spread, suppress its electrostatic impact on the channel, or decouple the work function from crystallographic randomness — each targeting a different stage in the variability chain from grain nucleation through to dielectric defect coupling.

Equiaxed grain deposition by RF-PVD

The most direct materials-level solution is to deposit the work function metal in a crystal structure where all grains are geometrically similar regardless of orientation. STMicroelectronics disclosed in a 2019 patent that depositing TiN via radio-frequency physical vapor deposition (RF-PVD) produces an equiaxed grain structure in which crystallographic anisotropy in the work function is substantially reduced. The patent states explicitly that “local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage,” and that the equiaxed structure “reduces local variability in threshold voltage.” This represents a manufacturable route that avoids compositional changes to the gate stack — a significant advantage for process integration.

Amorphous interlayer insertion (redundant silicon process)

Shanghai Huali Microelectronics has extensively patented a process in which a thin amorphous silicon (“redundant silicon”) layer is intercalated within the metal gate stack. A 5–50 Å layer is deposited between TiN and TaN layers and then annealed to form amorphous TiSiN and TaSiN silicide-nitride compounds. Because these compounds are inherently amorphous, they exhibit intrinsically lower work function spread than crystalline metal nitrides, while simultaneously blocking up-diffusion of metal atoms from overlying fill metals. A related Shanghai Huali patent (2016) provides the complementary process context in PMOS-region etch-back sequences, where TiN etch-process variation translates directly to TaN barrier residual-thickness variation and hence to NMOS Vt scatter. The introduction of the silicon barrier layer decouples the Vt from the TiN etch endpoint, reducing device-to-device mismatch.

Oxygen vacancy passivation in HfO₂ via compressive strain

At sub-5nm nodes, threshold voltage variability also has a contribution from the random distribution of oxygen vacancies (VO) in the HfO2 gate dielectric, which interact electrostatically with the metal gate grain boundaries. Vellore Institute of Technology proposed in a 2024 patent that applying compressive strain to HfO2 enhances the diffusivity of oxygen vacancies during device integration, enabling their passivation. Atomic simulations in the patent demonstrate that compressive strain in the high-k dielectric suppresses the random VO distribution and thereby directly reduces Vt variability from device to device — addressing the dielectric-side contribution to variability that is coupled to, and amplified by, the grain-boundary electrostatics of the metal gate above it. This coupling between grain arrangement and HfO2 defect chemistry was also identified by IBM in a 2016 patent, which disclosed a gate structure in which the concentration of oxygen vacancies in the high-k layer is controlled as a function of the work function granularity — a holistic approach to co-optimising metal gate and dielectric simultaneously, consistent with process integration frameworks described by NIST.

Architectural responses and circuit-level consequences

Threshold voltage tuning in HKMG CMOS has been addressed through implant-diffusion techniques as an alternative to the etch-based metal thickness control that inherently introduces granularity-driven variation. Multiple patents from the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS), propose depositing a dopant-containing sacrificial layer and annealing it to diffuse dopant atoms into the metal gate stack. The rationale stated in both the 2017 and 2020 IMECAS patents is that conventional TiNx-etch-based Vt adjustment has “poor controllability” and risks “process damage to the channel near the interface” — both of which are aggravated when grain-level inhomogeneity is present in the metal nitride. By substituting diffusion-controlled doping for etch-endpoint-dependent thickness, the process decouples Vt from the grain-boundary geometry of the metal film.

Texas Instruments holds an active European patent on processes for forming HKMG CMOS transistors with TiN gates, in which TiN thickness functions as the primary work function setter. This directly links deposition precision to Vt spread: any grain-boundary-induced thickness non-uniformity in TiN translates to a corresponding Vt offset, underscoring why grain texture control is a prerequisite for thickness-based Vt engineering. The connection between gate-metal deposition quality and device electrical performance has been further validated by noise-based characterisation studies from KU Leuven, which used low-frequency noise analysis to assess the impact of metal gate processing on gate oxide stack quality.

At the circuit-simulation level, variability in Vt induced by MGG propagates into power and timing uncertainty. The NCTU study on GAA CMOS circuits showed that WFV-induced Vt fluctuations directly modulate propagation delay and dynamic power dissipation in inverter chains, establishing that MGG is not merely a device-physics concern but a circuit-design constraint that must be budgeted at advanced nodes. This finding has direct implications for the static noise margin (SNM) of SRAM bitcells and the setup/hold time margins of flip-flops — both of which are σVt-sensitive. For circuit designers working at 5nm and below, the message is clear: grain-level crystallography of the gate metal is a first-order design variable, not a process detail to be handled upstream.

The University of Santiago de Compostela’s 2021 study added a metrology dimension: evaluating MGG as one of four variability sources in GAA NW FETs, the authors found that the threshold voltage extraction method itself introduces systematic offsets in σVt estimation. This is a practical challenge for process monitoring, statistical design kits, and yield prediction at 5nm and below — and it suggests that the industry’s standard characterisation infrastructure may underestimate the true magnitude of MGG-induced variability, a concern also flagged in reliability studies from Purdue University examining the dependence between time-zero and time-dependent variability in high-k NMOS transistors.

Key players and the evolution of innovation approaches

The patent and literature landscape reveals a clear bifurcation between academic modelling groups focused on analytical and TCAD characterisation of MGG physics, and industrial process-patent holders focused on manufacturable mitigation strategies. The dataset of approximately 50 patent and literature sources spans institutions across China, India, Korea, Taiwan, Spain, and the United States — reflecting the global nature of advanced CMOS process development.

Academic modelling leaders

• IIT Bombay (India, 2018): Leading contributor of closed-form MGG models for cylindrical nanowire geometry, using periodic boundary conditions and Poisson’s equation in cylindrical coordinates to quantify σVt as a function of grain count.
• POSTECH (Korea, 2022): Experimental decomposition of WFV, RDF, and geometry variation via error-propagation law and Pelgrom-plot analysis across multiple channel diameters.
• National Chiao Tung University (Taiwan, 2019 and 2014): Circuit-level variability propagation studies in GAA NW CMOS and 16nm FinFET, quantifying the path from grain crystallography to timing and power uncertainty.
• University of Santiago de Compostela (Spain, 2021): Metrology and statistical methodology — showing that extraction method choice introduces systematic offsets in σVt estimation for GAA NW FETs.

Industrial process-patent leaders

• Shanghai Huali Microelectronics (China): Highest single-assignee patent count on HKMG Vt-fluctuation reduction in the dataset. Active patents on redundant silicon process (2015), complementary PMOS etch-back sequences (2016), and amorphous top-cap barrier layers (2022).
• STMicroelectronics (2019): Equiaxed TiN RF-PVD process for direct grain-texture engineering to suppress WFV at its crystallographic source.
• IBM (2016): HKMG device with reduced Vt variation via co-optimisation of oxygen vacancy concentration and metal grain arrangement — a holistic gate-stack approach.
• Vellore Institute of Technology (2024): Newest filing explicitly targeting the sub-5nm regime, using compressive strain in HfO2 to passivate oxygen vacancies and reduce dielectric-side Vt dispersion.
• Institute of Microelectronics, Chinese Academy of Sciences (2017, 2020): Dopant-diffusion-based Vt adjustment as an alternative to etch-based metal thickness control, directly motivated by the poor controllability of granularity-sensitive TiNx etch processes.
• Texas Instruments (active EP): TiN thickness as work function setter in HKMG CMOS, directly linking deposition precision to Vt spread.

“Early-node patents address Vt tuning primarily through stack composition and thickness. Post-2018 literature and patents increasingly address grain-level crystallography and dielectric defect coupling as co-dominant variability sources, reflecting the industry’s arrival at the few-grain regime that academic models had long predicted.”

The trend across the dataset shows a clear evolution: early-node patents (pre-2016) address Vt tuning primarily through stack composition and thickness. Post-2018 literature and patents increasingly address grain-level crystallography and dielectric defect coupling as co-dominant variability sources — reflecting the industry’s arrival at the few-grain regime that academic models had long predicted. The 2024 VIT filing on sub-5nm strain engineering and the active Shanghai Huali patents on amorphous barrier layers represent the current frontier, where process and materials innovation must work in concert with device architecture to keep MGG-induced σVt within design budget. Tracking this evolving landscape is essential for R&D teams at semiconductor companies, as catalogued by organisations such as SIA in its annual industry roadmap updates.