The Staircase Principle: How More Voltage Levels Suppress Harmonics

Multi-level inverters reduce total harmonic distortion by generating a stepped output waveform: as the number of discrete voltage levels increases, each step becomes smaller and the waveform converges toward a pure sine wave, progressively diminishing the harmonic energy present in the output. Traditional two-level inverter topologies suffer from inherent power quality limitations that force the use of bulky transformers and harmonic filters, whereas MLI structures inherently reduce THD through their stepped waveform generation, enabling operation at lower switching frequencies with fewer filtering requirements — a finding confirmed by reviews from both Nisantasi University, Istanbul (2022) and Texas Tech University (2022).

The physical mechanism is straightforward: in a conventional two-level inverter, the entire DC-bus voltage is switched hard across a single bridge, generating large voltage transients that are rich in high-amplitude harmonics. A five-level diode-clamped topology, by contrast, distributes voltage stress across multiple semiconductor stages and generates the output waveform at low switching frequency with inherently low distortion — as demonstrated by research from Yangon Technological University (2020). The staircase waveform eliminates the concentration of switching transients that is the root cause of harmonic generation in conventional designs.

The quantitative relationship between level count and harmonic suppression has been confirmed empirically. Research from Kakatiya Institute of Technology and Science, Warangal (2022) demonstrates through simulation that a 127-level MLI achieves dramatically lower THD compared to 15-level, 31-level, and 63-level configurations — confirming the monotonic inverse relationship between level count and harmonic distortion. Taizhou University, China (2021) makes the trade-off explicit: adding large filter elements can reduce THD in conventional MLIs, but adding output levels achieves the same goal with reduced size and cost, making the topological approach superior for solar PV applications.

Topology Architectures and Their THD Performance

Different multi-level inverter architectures achieve harmonic suppression through distinct physical mechanisms, and each presents specific trade-offs in component count, isolation requirements, and suitability for solar PV source characteristics. The three dominant families — cascaded H-bridge (CHB), neutral point clamped (NPC), and switched capacitor (SC) — have each been extensively characterised for grid-tied solar applications in the dataset.

Cascaded H-Bridge (CHB) Topologies

The cascaded H-bridge remains the most widely referenced architecture for solar PV MLI applications due to its modularity and natural fit with multiple PV string sources. The topology’s modular cascaded stages distribute harmonic generation across multiple switching events, reducing per-level voltage jumps. A reduced-switch seven-level cascaded inverter (RSCI) with repetitive control, demonstrated by SOA University, India (2018), achieves enhanced power quality for active and reactive power control in a grid-connected PV-battery microgrid. Asymmetric CHB configurations — where DC source voltages are set in binary or trinary ratios rather than equal values — deliver a disproportionately high number of output levels for a given switch count. Research from I. K. Gujral Punjab Technical University (2022) shows that an asymmetric 15-level inverter using only seven unidirectional switches and three symmetric DC sources achieves significant harmonic reduction in a grid-connected solar PV system, with the asymmetric source arrangement generating 7-, 11-, or 15-level outputs through source magnitude selection alone.

Neutral Point Clamped (NPC) Topologies

NPC inverters clamp intermediate voltage levels using diodes tied to a DC-link midpoint, enabling three- or multi-level output without multiple isolated sources. A three-level NPC inverter produces comparatively fewer harmonics and increases power delivery compared to conventional two-level inverters when applied to a 250 kW grid-connected solar PV array — as demonstrated in a 2019 study on effective modulation schemes. Extending this architecture to a 15-level NPC inverter, Deakin University, Australia (2021) demonstrates that a proportional-integral resonant controller with harmonic and lead compensator (PIR + HC + LC) further suppresses residual harmonic content in the grid current beyond what the topology alone provides, highlighting the importance of controller co-design.

Switched Capacitor (SC) Topologies

SC-based MLIs are increasingly prominent in solar applications due to their transformer-less and inductor-less operation — a critical advantage for microinverter size constraints. According to a review from Vellore Institute of Technology (2023), SC-MLIs offer enhanced voltage regulation within the capacitor itself and significantly reduced electromagnetic interference, both of which contribute to lower injected harmonic content at the grid connection point. A 2022 Indian patent by MR. GURUMURTHY NAGIREDLA discloses an SC topology with reduced input capacitance that simultaneously improves overall voltage gain and reduces THD for solar panel applications, operating at low switching frequency to minimise transient stress.

“Adding output levels achieves the same THD reduction as large filter elements — with reduced size and cost — making the topological approach superior for solar PV applications.”

Modulation Strategies and Control Techniques for THD Minimisation

Topology alone does not determine THD in a grid-tied solar MLI — the switching pattern applied to the power devices has an equally decisive role, and the correct modulation strategy must be selected for each specific topology architecture. Multiple modulation strategies have been evaluated and optimised specifically for grid-tied solar MLI designs across the dataset.

Selective Harmonic Elimination (SHE) and SPWM

Selective harmonic elimination precomputes switching angles to cancel specific low-order harmonics — particularly the dominant 5th, 7th, 11th, and 13th — that are most problematic for grid compliance. The University of Bologna (2016) reformulates the THD minimisation problem in the time domain rather than the frequency domain, enabling consideration of all switching harmonics simultaneously and yielding optimal switching angles that minimise both voltage and current THD — addressing a fundamental limitation of frequency-domain methods that only target a limited number of harmonics. A 2022 patent from Lovely Professional University, India, specifically claims optimal selective harmonic elimination PWM for an asymmetric MLI integrated with a grid-connected solar PV system.

Phase-Shifted and Level-Shifted PWM

For CHB and cascaded SC topologies, phase-shifted PWM (PS-PWM) distributes switching events uniformly across cascaded modules, effectively shifting harmonic energy to higher frequencies where it is easier to filter. Harbin Institute of Technology, Shenzhen (2021) proposes a hybrid modulation strategy combining level-shifted PWM (LS-PWM) and PS-PWM that automatically balances both inter-module power sharing and intra-module capacitor voltages, producing an optimised capacitor voltage ripple that enables smaller capacitors with better output voltage waveforms — directly reducing THD. Research from Arunai Engineering College (2016) compares PDPWM, PODPWM, APODPWM, VFPWM, and COPWM for a nine-level inverter, finding that PODPWM provides the lowest THD value and COPWM provides the highest fundamental RMS output voltage — confirming that modulation scheme selection is topology-dependent and must be co-optimised with the switching architecture.

Advanced Closed-Loop Controllers

Grid-tied microinverters require active current control to maintain THD compliance under varying irradiance, grid voltage distortion, and load conditions. According to IEEE standards including IEEE 519, the injected current THD must remain below 5% at the point of common coupling across all operating conditions — a requirement that passive topology alone cannot guarantee under real-world grid disturbances. Deakin University (2021) demonstrates that a PIR controller with harmonic and lead compensators outperforms conventional PI control in a 15-level NPC MLI by providing infinite gain at targeted harmonic frequencies, enabling zero steady-state tracking error for both fundamental and harmonic reference currents. Konkuk University, Seoul (2018) applies repetitive control in a synchronous reference frame to a dual-buck PV inverter, significantly reducing THD in both continuous and discontinuous conduction modes — demonstrating that harmonics in this architecture are predominantly odd-order, a characteristic exploitable by the SRF controller through Park’s transformation.

For grid-tied systems under distorted grid voltage conditions, Seoul National University of Science and Technology (2016) proposes a dual-controller scheme that independently controls fundamental and harmonic current components through a PI decoupling controller and a predictive basis controller, maintaining THD compliance even when the grid itself contains harmonic voltage distortion — a real-world condition increasingly common as distributed generation penetration rises, as noted by WIPO in its reporting on power electronics IP trends.

From Lab to Rooftop: MLI in Solar Microinverter Designs

Microinverters — module-level power electronics mounted directly behind individual PV panels — impose unique constraints on MLI topology selection that distinguish them from string or central inverter designs. Extreme size and weight restrictions, wide input voltage variation from a single panel, the need for galvanic isolation in some jurisdictions, and the requirement for THD compliance at rated and partial load conditions all shape topology and control choices.

Research from Maulana Azad National Institute of Technology, Bhopal (2020) investigates a micro multilevel inverter structure where a five-level inverter is fitted beneath each pair of solar panels. Level-shifting SPWM controls the five switches, and the study demonstrates that output THD varies with modulation index, providing a design curve for THD optimisation at different irradiance conditions — a critical insight for systems operating across wide irradiance ranges.

The most precise THD figure in the dataset comes from Pohang University of Science and Technology, Korea (2019): a 320 W single-stage microinverter using an interleaved boost converter combined with a full-bridge converter and voltage doubler achieves a THD of 2.65% at rated power. Variable switching frequency and advanced burst control schemes further shape the harmonic spectrum to comply with grid standards, while maintaining a CEC weighted efficiency of 95.55%. This demonstrates that sub-3% THD is achievable in practical microinverter hardware at module-level power ratings.

“A 320 W solar microinverter achieved 2.65% THD at rated power with a CEC weighted efficiency of 95.55% — demonstrating that sub-3% harmonic distortion is achievable in practical module-level hardware.”

University of Nariño, Colombia (2021) implements a dual-stage solar microinverter — an active clamp flyback DC-DC stage followed by a dual-buck DC-AC stage — with dq-transformation-based control loops that regulate voltage, current, and phase simultaneously. The mathematical decoupling provided by the dq control minimises harmonic injection into the grid by ensuring that the current reference tracking error — the primary source of harmonic generation in actively controlled inverters — is reduced to near zero.

The most direct regulatory compliance data in the dataset comes from a 2019 grid-tied MLI study: THD in the point-of-common-coupling voltage is reduced from 13% to below 5% (the IEEE 519 requirement) through the combination of the multilevel topology and an output filter, while grid current THD drops from 14.8% to below 5%. For nonlinear loads, similar reductions are achieved, confirming that the topology-plus-filter combination satisfies regulatory requirements across load types. Standards bodies including IEC and IEEE continue to tighten harmonic injection limits as distributed solar penetration increases, making these compliance margins increasingly important for product certification.

Innovation Landscape: Key Players and Emerging Trends

Analysis of more than 60 patents and research publications spanning 2013–2023 reveals clear institutional and geographic concentrations of MLI-for-solar research activity, with four dominant trends shaping the next generation of grid-tied microinverter designs.

India is the most prolific contributor, with high-output institutions including IIT Delhi, IIT Bombay, Vellore Institute of Technology, NIT Warangal, and multiple other NITs and engineering colleges. Indian patent applications — including the switched capacitor MLI patent from MR. GURUMURTHY NAGIREDLA and the asymmetric MLI patent from Lovely Professional University — indicate growing IP activity beyond academic publication. South Korea contributes high-impact work on control strategies, with Pohang University of Science and Technology, Konkuk University, and Seoul National University of Science and Technology focusing on harmonic extraction and grid compliance under distorted conditions. South America, particularly Universidad de Talca in Chile, is a growing hub with multiple papers on reduced-switch topologies and microinverter control. China contributes significantly through Harbin Institute of Technology Shenzhen and Taizhou University. European contributions include the University of Bologna (Italy) on time-domain THD optimisation, Universitat Politècnica de València, Deakin University (Australia), and the University of Galati (Romania) on MPC-based PUC topologies.

According to WIPO global patent data, power electronics for renewable energy represents one of the fastest-growing technology areas in international patent filings, consistent with the dataset’s geographic and institutional diversity. Four innovation trends are particularly prominent:

• Switch count minimisation: achieving more output levels with fewer semiconductor components is the primary cost driver for microinverter economics, and asymmetric source configurations that geometrically expand level count without proportional hardware increases are the leading approach.
• Transformer-less and filter-less designs: high-level count topologies — particularly switched capacitor architectures — enable operation without bulky passive components, directly addressing microinverter size and weight constraints.
• Intelligent modulation and control co-design: topology and controller are increasingly jointly optimised for THD compliance under real-world grid and irradiance conditions, moving beyond the traditional separation of hardware and software design phases.
• Multifunctional microinverter integration: research from Universidade do Minho, Portugal (2020) demonstrates a microinverter that simultaneously injects PV power into the grid and charges a battery storage system, maintaining low-THD grid injection across all operating modes — a convergence of energy storage and power quality functions that reflects broader industry trends tracked by the IEA.

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