Why SiC Switching Destroys Cable Insulation: The Physics of PDIV Degradation

Partial discharge inception voltage (PDIV) degradation in medium-voltage cable insulation is driven primarily by the high dv/dt of SiC MOSFET switching transitions, which often exceeds hundreds of V/ns, producing reflected-wave overvoltages at cable terminations that repeatedly challenge and erode the insulation’s inception threshold. This is not a simple amplitude problem — it is a waveform-physics problem, and understanding the distinction is the prerequisite for selecting effective countermeasures.

Research from the University of Manchester (2021) analysed two-level, three-level, and quasi-three-level PWM waveforms and showed that the electric field distribution inside insulation defects is directly tied to the shape of the applied pulse waveform. PDIV degradation is therefore waveform-dependent rather than merely amplitude-dependent — a finding that fundamentally changes how engineers must approach insulation qualification testing for SiC-fed drives.

The reflected-wave phenomenon compounds this problem significantly in cable-fed systems. As established by the University of Bristol (2022), switching rise and fall times — which vary with load current and SiC MOSFET parasitic elements — are the key parameter governing the magnitude of motor overvoltage, resulting in a non-uniform overvoltage envelope under standard two-level converter operation. This non-uniformity means that PDIV thresholds are repeatedly challenged in a statistically unpredictable manner, accelerating insulation aging in ways that deterministic test protocols cannot fully capture.

The degradation mechanism becomes self-reinforcing through impulse-initiated PD persistence. Research from Delft University of Technology (2019) demonstrated that impulse transients — closely analogous to SiC switching pulses — can initiate PD in insulation defects even below the nominal AC inception voltage, and that once initiated, such PD activity can persist under subsequent AC voltage cycles. In SiC-fed MV cable systems where transient pulses are applied at PWM frequency (potentially tens of kilohertz), this persistent PD has no time to self-extinguish between pulses, creating a continuous degradation pathway.

Empirical data from the University of Texas at Austin (2017) on semicon-insulation interface defects — the most common real-world defect type in MV cables — confirmed that PDIV and PD repetition rate change substantially between AC and DC excitation conditions. The complex pulsed waveform generated by an SiC inverter therefore creates a unique insulation stress environment that cannot be characterised from sinusoidal test data alone, invalidating conventional cable qualification approaches for SiC-driven applications.

“Impulse transients can initiate partial discharge in cable insulation defects even below the nominal AC inception voltage — and once initiated, this PD persists under subsequent AC cycles, establishing a self-reinforcing degradation process.”

Output Filter Design and dv/dt Slew-Rate Control: The First Line of Defence

The most direct engineering intervention for reducing PDIV degradation is to prevent high-dv/dt pulses from reaching the cable insulation in the first place — through passive LRC output filters, active dv/dt profiling circuits, or snubber networks that absorb the reflected energy before it reaches the cable termination.

Chalmers University of Technology (2022) established a systematic design methodology for LRC passive filters to suppress the voltage reflection phenomenon in SiC-based motor drives. The methodology begins with an equivalent circuit model of long cables, then derives filter parameters based on the high-frequency behaviour of the cable. In applications such as oil fields and aircraft — where cable lengths may exceed hundreds of metres — the voltage reflection problem is severe enough to directly threaten motor insulation life. The proposed filter design approach provides quantified suppression of the reflected overvoltage, giving engineers a structured path from cable characterisation to filter specification.

A more sophisticated approach — one that avoids the efficiency penalty of conventional gate resistance increases — is soft-switching dv/dt profiling, demonstrated by State Grid Shanghai Energy Internet Research Institute (2022). This approach optimises the rise and fall time of the output voltage according to cable length, without altering the intrinsic switching speed of the SiC devices. The key innovation is that voltage slew-rate profiling is implemented via a soft-switching auxiliary circuit that recovers energy rather than dissipating it, preserving the efficiency advantage of SiC technology while substantially reducing the insulation stress imposed on the cable. This decoupling of slew-rate control from switching speed is the defining feature that distinguishes this approach from simple gate resistor increases.

Snubber-based overvoltage mitigation provides a third pathway. Roma Tre University (2021) demonstrated that adding snubber circuits — consisting of capacitors and diodes — to SiC inverter switches mitigates overvoltage without sacrificing conversion efficiency, provided that an energy recovery circuit is included. The study experimentally validated this approach on a converter prototype, confirming that snubber-based overvoltage mitigation is a viable route to reducing the peak voltages that challenge cable PDIV thresholds, particularly in retrofit scenarios where inverter topology changes are not feasible.

PWM modulation strategy is also a direct lever on PDIV exceedance frequency. The University of Manchester (2021) demonstrated that three-level and quasi-three-level PWM waveforms produce fundamentally different electric field histories inside insulation defects compared to two-level PWM, with the multi-level approaches reducing the number and severity of PD events per fundamental cycle. Selecting a three-level inverter topology or quasi-three-level modulation reduces the amplitude of voltage steps applied to the cable insulation and thereby reduces the frequency with which PDIV is exceeded — a topology-level intervention that addresses the root cause rather than its downstream effects. Standards bodies including IEC are increasingly incorporating PWM waveform considerations into insulation qualification frameworks for inverter-fed drives.

Power Module Packaging and Electric Field Management: The Upstream Risk Factor

A critical and frequently underappreciated source of PDIV degradation in medium-voltage SiC systems is the power module package itself, where high electric fields can initiate partial discharges that are distinct from — and additive to — the stress imposed on the cable insulation. Addressing this upstream source is a prerequisite for comprehensive PDIV management.

Virginia Tech’s Center for Power Electronics Systems (2020) directly quantified this issue in their 10-kV SiC MOSFET power module research, noting that existing power module packages are unable to address the detrimental EMI and partial discharge challenges that result from high-speed, high-voltage switching, which limits converter operation. Their proposed 10-kV SiC module packaging redesign addresses electric field distribution, EMI, and thermal management simultaneously, with the explicit goal of preventing partial discharge from arising within the module package — a source of PDIV degradation that is upstream of the cable system entirely.

This packaging-level challenge was identified even earlier in the same group’s 2017 work, which established that high-density packaging of high-voltage SiC power semiconductors requires low electric field concentration to prevent premature dielectric breakdown. That study reported the first detailed optimisation of a high-voltage SiC MOSFET power module, incorporating electric field analysis as a co-equal design objective alongside electromagnetic, thermal, and mechanical analyses. The framework established there — treating electrostatic field distribution as a primary packaging design constraint — has since become the standard approach for MV SiC module development, and is referenced by subsequent work from institutions including IEEE member groups worldwide.

The broader system-level context is provided by the University of Stuttgart (2022), whose comprehensive review of inverter-fed traction machine insulation establishes that wide bandgap semiconductor devices, combined with increasing DC link voltage, expose the winding insulation system to enhanced electrical stress. The review’s most consequential finding for cable system engineers is that simply increasing insulation thickness is not a sufficient countermeasure when pulsed voltage is applied, because PDIV under repetitive pulsed voltage does not scale in the same way as it does under sinusoidal excitation. This finding directly undermines the conventional engineering response of merely adding insulation thickness to cables, and mandates a field-based design approach instead.

“High electric fields in inadequately designed SiC module packages initiate partial discharges that are distinct from — and additive to — the cable insulation stress. Power module packaging is an upstream source of PDIV risk that must be addressed before cable-level mitigations can be fully effective.”

PD-Free Insulation Design: Paschen’s Law, FEM Analysis, and the Limits of Conventional Testing

The most robust long-term protection against PDIV degradation in medium-voltage SiC cable systems is PD-free design — an approach that uses electrostatic finite element modelling combined with Paschen’s law to ensure that electric fields in all insulation voids remain below inception thresholds under worst-case inverter operating conditions, rather than attempting to manage PD after it has been initiated.

The University of Nottingham Ningbo China (2019) demonstrated the application of Paschen’s law for air combined with electrostatic FEM to determine the electric field at the turn-to-turn insulation interface and define the geometry and material thickness required to ensure PD-free operation. Although developed for low-voltage machines, the methodology — combining FEM field analysis with Paschen thresholds — is directly transferable to MV cable insulation design. The key output is a geometry specification that guarantees the electric field in all air voids remains below the Paschen breakdown threshold under all operating conditions, eliminating PD initiation rather than attempting to arrest it after the fact.

Florida State University (2021) extended this framework to electrified aircraft — an application where altitude-dependent air pressure reduces the Paschen breakdown threshold, compressing the PDIV margin significantly. The paper proposes an optimised insulation system design that can provide the specified service life at the chosen failure probability while also potentially eliminating the risk of partial discharges entirely. The methodology covers turn, phase-to-ground, and phase-to-phase insulation subsystems, and its treatment of how operating conditions shift PD probability is directly applicable to the variable-amplitude, variable-frequency stress imposed by SiC inverters on MV cable systems. Research published by Nature and affiliated journals on dielectric breakdown physics underpins the Paschen modelling framework used in this approach.

The persistence mechanism identified by Delft University of Technology (2020) is particularly significant for design specification purposes. Their study found that impulse voltages and superimposed transients initiate PD in artificial cable joint defects even when the applied voltage is below the nominal AC inception voltage, and that under certain electric field conditions these PDs persist after the transient has passed. In SiC-fed MV cable systems where transient pulses are applied at PWM frequency — potentially tens of kilohertz — persistent PD has no time to self-extinguish between pulses. This finding establishes that the design target for MV cable insulation in SiC-driven systems must be a field level below the impulse-initiated PD threshold, not merely below the sinusoidal AC PDIV — a substantially more demanding specification.

The empirical data from the University of Texas at Austin (2017) on semicon-insulation interface defects reinforces this conclusion. PDIV and PD repetition rate change substantially between AC and DC excitation conditions, confirming that the complex pulsed waveform generated by an SiC inverter creates a unique insulation stress environment that standard sinusoidal qualification tests cannot characterise. Cable insulation systems for SiC-driven MV applications therefore require bespoke qualification protocols that replicate the actual inverter waveform — a requirement that standards bodies including IEC are beginning to address in updated test standards for inverter-fed drive systems.

Research Landscape: Leading Institutions and Innovation Trends

The research dataset of more than 50 literature sources and patents reveals a concentrated set of institutions driving innovation across the four mitigation categories, with distinct specialisations that define the state of the art in each area.

Power Module Packaging and Electric Field Co-Optimisation

Virginia Tech’s Center for Power Electronics Systems (CPES) leads globally in high-voltage SiC power module packaging with integrated electric field management. Their 2017 and 2020 publications uniquely integrate electromagnetic, thermal, mechanical, and electrostatic field co-optimisation, setting the standard for MV SiC module design. Their work on the 10-kV SiC MOSFET module directly addresses the packaging-level PDIV risk that is upstream of the cable insulation system.

Experimental PD Characterisation Under Transient Conditions

Delft University of Technology leads in experimental characterisation of PD behaviour in XLPE cable insulation under transient and impulse conditions, as demonstrated by their 2019 and 2020 publications. Their research directly quantifies the PD persistence risk from inverter switching pulses and establishes the impulse-initiated PD threshold as the correct design target for SiC-fed MV cable systems — a more demanding specification than the conventional sinusoidal PDIV.

PWM Waveform Analysis and Topology Selection

The University of Manchester leads in PWM waveform-level analysis of PD behaviour in SiC-driven motor insulation systems. Their 2021 work bridges inverter topology selection and insulation stress quantification, providing the direct experimental evidence that three-level and quasi-three-level PWM topologies reduce PD event frequency and severity compared to two-level operation.

Control-Domain Mitigation and Parasitic Interaction

The University of Bristol and State Grid Shanghai Energy Internet Research Institute represent the leading groups in control-domain mitigation — specifically soft-switching dv/dt profiling and analysis of how parasitic elements interact with cable overvoltage. Their 2022 publications together establish the theoretical and practical basis for decoupling slew-rate control from switching speed in SiC-based drives.

Insulation System Optimisation Methodology

Florida State University’s Center for Advanced Power Systems is the dominant contributor for insulation system optimisation methodology in high-performance and safety-critical drive applications. Their 2021 work on electrified aircraft insulation design provides the most complete published treatment of how to apply Paschen-based FEM analysis to ensure PD-free operation under variable-amplitude, variable-frequency inverter stress — a methodology directly applicable to MV cable systems driven by SiC inverters. This work is complemented by the University of Nottingham Ningbo China’s 2019 foundational work on PD-free machine design using the same FEM-Paschen framework. The broader innovation intelligence picture for this field is accessible through PatSnap’s R&D intelligence platform, which tracks patent filings and literature across all four mitigation categories.

The innovation trend across all institutions points toward system-level co-optimisation: no single mitigation strategy is sufficient in isolation. The most robust approaches combine output filter design, soft-switching dv/dt profiling, multi-level PWM topology, electric field-aware module packaging, and Paschen-based FEM insulation design as a coordinated system. The PatSnap Insights blog tracks ongoing developments in SiC power electronics and insulation engineering across all of these dimensions.