How phase change memory stores data — and why resistance contrast matters
Phase change memory (PCM), also known as PCRAM or PRAM, stores data by exploiting the reversible electrical resistance contrast between the crystalline and amorphous states of chalcogenide materials — principally germanium-antimony-tellurium (GST) alloys. The resistance contrast between the low-resistance crystalline SET state and the high-resistance amorphous RESET state is typically 3–4 orders of magnitude, enabling reliable binary data storage without continuous power.
The core write mechanism involves two distinct electrical pulses applied to a GST layer sandwiched between electrodes. A high-amplitude, short-duration RESET pulse melts and rapidly quenches the material into the amorphous state. A lower-amplitude, longer-duration SET pulse anneals it back to the crystalline phase. Controlling the nucleation and crystal growth stages of this transition is a persistent engineering challenge — one Intel addressed in a 2025 filing introducing a nucleation-then-crystal-growth two-stage SET algorithm using distinct current levels over multiple time periods.
Chalcogenide materials are compounds containing one or more chalcogen elements (sulfur, selenium, or tellurium). In PCM, the principal chalcogenide is Ge₂Sb₂Te₅ (GST) — a germanium-antimony-tellurium alloy whose atomic structure can be reversibly switched between ordered crystalline and disordered amorphous configurations by Joule heating, enabling the resistance contrast that underpins data storage.
The technology’s non-volatile character — it holds state without power — positions it between DRAM (fast but volatile) and NAND flash (persistent but slow) in the memory hierarchy. This gap, known as storage-class memory, is one of the primary commercial targets for PCM in 2026. According to WIPO, non-volatile memory technologies including PCM are among the most actively patented semiconductor sub-domains globally, reflecting sustained industrial investment across the memory hierarchy.
Phase change memory (PCM) stores binary data by switching chalcogenide GST alloys between a low-resistance crystalline state and a high-resistance amorphous state, with a resistance contrast of typically 3–4 orders of magnitude, enabling non-volatile data retention without continuous power.
Who owns the PCM patent landscape: Samsung, IBM, Intel, and beyond
Samsung Electronics is the single largest PCM assignee in the PatSnap dataset, with more than 15 distinct patent entries spanning cell architecture, materials engineering, multilevel cell (MLC) operation, circuit design, and system integration across Korean and Japanese jurisdictions — a breadth that reflects Samsung’s vertically integrated position from material to product. Any entrant into this space faces a dense Samsung IP thicket across KR and JP jurisdictions; freedom-to-operate analysis in Korea is essential before commercial product development.
The most active academic assignee is Hanyang University IUCF (IUCF-HYU), with at least 7 filings concentrated in the 2015–2022 period, focused on 3D crossbar architecture, ovonic threshold switching (OTS) selector integration, selector-unified cells, neuromorphic applications, and discharge circuit design. This signals a strong university-industry pipeline in Korea that represents a licensable technology cluster for 3D crossbar PCM arrays.
IBM has maintained consistent long-term investment with three dataset entries: the Peltier-cooled PCM cell (2008), gradual-reset structures for analog compute (2023/2025), and the PCM+MRAM AI accelerator (2024) — demonstrating a deliberate pivot toward neuromorphic and AI hardware. HGST Netherlands (a Western Digital entity) filed a cluster of 5 closely related storage-class memory system patents across JP and KR jurisdictions between 2014 and 2016. Several of these filings are now inactive, according to EPO legal status records, creating potential white space for new system architecture IP.
Samsung Electronics holds the broadest PCM IP position in the PatSnap dataset with more than 15 distinct patent entries spanning cell architecture, materials engineering, MLC operation, circuit design, and system integration across Korean and Japanese jurisdictions, spanning more than two decades of filings from 2005 to 2021.
Map the full PCM patent landscape — assignees, claims, and legal status — with PatSnap Eureka.
Explore PCM Patents in PatSnap Eureka →Four device architecture clusters driving PCM innovation
PCM innovation within the dataset organises into four distinct engineering clusters, each addressing a different constraint on device performance, density, or system deployability. Understanding these clusters is essential for freedom-to-operate analysis and for identifying where genuine white space exists.
Cluster 1: Mushroom/pillar cell with electrode engineering
The dominant historical architecture places a GST phase-change layer between a bottom heating electrode (typically TiN) and a top electrode, confining the active switching volume to the small contact region above the heater plug. A key innovation vector has been thermoelectric electrode asymmetry — using N-type and P-type thermoelectric materials for the lower and upper electrodes to reduce reset current via the Seebeck effect. Samsung Electronics demonstrated this approach in a 2006 KR filing using thermoelectric electrode pairs with mismatched Seebeck coefficients to directionally bias heat flow. Korea Institute of Science and Technology (KIST) combined a high-thermal-conductivity AlN lateral heat-sink layer with a low-thermal-conductivity TiN heater electrode in a 2011 JP filing, enabling low-current high-speed operation.
Cluster 2: Chalcogenide doping and novel material compositions
Modifying the GST baseline through controlled doping of insulating impurities, nitrogen, or antimony-rich phases — or substituting entirely new chalcogenide families — is a persistent approach to improving set-state stability, resistance window, and endurance. Samsung’s 2007 JP filing distributes insulating impurities at ≤10% volume uniformly within the GST matrix to narrow resistance distributions and improve endurance. ETRI’s 2009 JP filing uses Ge₂Sb₂₊ₓTe₅ (0.12≤x≤0.32) to force a direct amorphous-to-single-phase-crystalline transition, improving set-state stability. The University of Southampton proposed gallium-lanthanum-sulfide (GLS) chalcogenide compounds with 3–5 dB lower optical volatility than GST in a 2008 KR filing, broadening the material design space.
Cluster 3: 3D crossbar arrays with integrated selectors
High-density integration requires a selector element co-located with each PCM cell to suppress sneak-path leakage in crossbar arrays. Two main selector strategies appear in the dataset: OTS-based selectors and PN-junction semiconductor selectors integrated within the phase-change layer itself. Hanyang University IUCF deployed OTS layers perpendicular to PCM layers in a true 3D crossbar in a 2018 KR filing, minimising the PCM-OTS contact area to reduce switching currents. A complementary 2018 KR filing from the same group introduced a transition-metal-compound selector within the PCM layer itself — exhibiting high resistivity in the crystalline state and low resistivity in the amorphous state — enabling a selector-unified cell without a separate OTS layer.
Cluster 4: System-level storage-class memory and AI integration
PCM is being deployed beyond standalone embedded memory into tiered memory systems bridging DRAM and NAND flash, and — most recently — as an analog compute element in AI accelerators. HGST Netherlands defined the enhanced storage-class memory (eSCM) architecture in a 2014 JP filing, combining DRAM DIMMs with PCM/ReRAM/STT-RAM managed by a dedicated processor for data allocation by dataset size. Intel’s 2018 CN filing maps NVM including PCM directly into the system address space as persistent main memory with volatile DRAM as a memory-side cache.
“PCM’s future competitive differentiation lies in analog in-memory computing rather than as a binary NVM commodity — R&D teams should prioritise analog conductance precision and write algorithm IP.”
From storage-class memory to AI accelerators: where PCM is being deployed
PCM’s application domains span four distinct use cases in the 2026 dataset, each at a different stage of commercial maturity and each making different demands on the underlying device physics.
Storage-class memory for servers and data centres
The most commercially mature application in the dataset is tiered memory hierarchy for servers and data centres. HGST Netherlands filed a cluster of 5 closely related patents across JP and KR jurisdictions (2014–2016) on eSCM DIMM cards incorporating PCM alongside DRAM and NAND flash, managed by a dedicated eSCM processor that allocates data by dataset size. Intel’s persistent cache architecture (2018, CN) and multi-level memory direct-access patent (2017, KR) extend PCM use into persistent main memory as a DRAM alternative. Shandong University’s filing on paging, ECC, and multi-bit prefetch methods for PCM (2015, CN) addresses software-level system management for large-capacity PCM storage arrays. As noted by IEEE, storage-class memory architectures bridging DRAM and flash remain an active area of standards development and commercial deployment.
Neuromorphic computing and AI inference
PCM’s analog resistance programmability and device-level nonlinearity make it a natural fit for neuromorphic circuit emulation. Hanyang University IUCF’s 2015 KR filing uses arrays of phase-change layers connected through switching devices to emulate neural soma integration. IBM’s 2024 AI accelerator patent co-integrates PCM and MRAM at the same metal level for in-memory analog inference, exploiting PCM’s analog conductance states for matrix-vector multiply operations — the core computation in neural network inference.
IBM’s 2024 AI accelerator patent (filed in Japan) co-integrates PCM and MRAM at the same metal level to perform in-memory analog matrix-vector multiply operations, exploiting PCM’s analog conductance states for neural network inference without moving data off-chip.
Embedded NVM and consumer electronics
Early Samsung and SK Hynix filings (2005–2010, KR) targeted PCM as a NOR flash replacement in mobile devices, emphasising low-current operation, page-mode read, and prefetch architectures. SK Hynix’s fusion memory device concept (2011, KR) places two PCM groups with different resistance distributions on one chip to simultaneously emulate DRAM and flash functionality — a single-chip solution for devices requiring both volatile and persistent storage.
Multilevel cell (MLC) storage density
Multiple assignees have pursued MLC operation (2–4 bits per cell) using parallel or series dual-layer PCM stacks, variable voltage/current driving, and advanced coding schemes. Industrial Technology Research Institute (Taiwan) filed on multilevel PCM in 2006 (JP). POSTECH Academy-Industry Foundation addressed data coding for MLC PCM in a 2016 KR filing. MLC capability is a prerequisite for PCM’s competitive viability against 3D NAND flash in storage-class memory applications.
Need to identify white space in PCM application domains before your next R&D investment decision?
Analyse PCM Application Patents in PatSnap Eureka →Frontier directions: vertical 3D, analog compute, and back-end integration
The most recent filings in the dataset (2022–2026) point toward four distinct frontier directions, each representing a qualitative shift in how PCM is engineered and where it is deployed.
1. Vertical 3D integration with back-end oxide semiconductor selectors
TSMC’s January 2026 filing describes a vertical PCRAM device where an oxide semiconductor layer serves as the gating element for the phase-change resistor stack, integrated within the back-end metallization layers above the device layer. This represents a shift from conventional front-end-of-line PCM cell integration to a fully back-end embedded NVM paradigm compatible with advanced logic process nodes — a process-integration milestone that could redefine embedded NVM competitive dynamics for fabless companies and IDMs alike.
TSMC’s January 2026 CN filing on vertical PCRAM integrates an oxide semiconductor transistor selector within the back-end metallization stack — eliminating the need for front-end process changes. IP strategists at fabless companies and IDMs should monitor TSMC’s continuation filings in this area closely, as this approach could enable embedded PCM in advanced logic nodes without front-end process disruption.
2. Analog PCM for AI in-memory computing
IBM’s 2024 AI accelerator patent explicitly targets analog conductance states of PCM for matrix-vector multiply operations, co-integrating PCM and MRAM at the same metal level. The gradual-reset structure patents (2023 and 2025, JP) from IBM provide the device-level precision required for multi-level analog weight storage. These filings collectively constitute a coherent IBM IP cluster aimed at practical in-memory inference hardware.
3. Multi-step write algorithms for SET reliability
Intel’s 2025 filing introduces a nucleation-then-crystal-growth two-stage SET algorithm using distinct current levels over multiple time periods, targeting write latency improvement and long-term resistance stability. This is a critical issue for MLC and analog PCM applications, where resistance precision directly determines inference accuracy or storage density. The filing signals that write algorithm IP — not just device architecture — is becoming a key competitive differentiator.
4. Advanced OTS selector and discharge circuit design for 3D arrays
Hanyang University IUCF’s 2022 filings address a practical read-disturb problem in OTS-selected 3D PRAM arrays through feedforward and GGNMOS-based discharge circuits, reflecting maturation of 3D integration challenges toward array-level reliability engineering. This work signals that the 3D crossbar architecture is approaching the reliability threshold required for commercial deployment.
Strategic implications for IP and R&D teams
The PCM patent landscape in 2026 presents distinct strategic challenges and opportunities depending on whether an organisation is a materials innovator, a device architect, a system integrator, or an AI hardware developer. Five implications stand out from the dataset.
Samsung’s IP thicket demands early freedom-to-operate analysis. Samsung Electronics holds the broadest PCM IP position in the dataset, spanning materials, cell architecture, circuit design, and system integration across more than two decades of KR and JP filings. Any entrant into this space must conduct freedom-to-operate analysis in Korea before commercial product development.
The AI/neuromorphic vector is the highest-growth frontier. IBM’s 2023–2025 cluster of gradual-reset and AI accelerator filings, combined with Intel’s multi-step SET algorithm work, signals that PCM’s future competitive differentiation lies in analog in-memory computing rather than as a binary NVM commodity. R&D teams should prioritise analog conductance precision and write algorithm IP.
TSMC’s 2026 back-end vertical PCRAM filing is a process-integration milestone. IP strategists at fabless companies and IDMs should monitor TSMC’s continuation filings in this area, as this approach could enable embedded PCM in advanced logic nodes without front-end process disruption — potentially redefining embedded NVM competitive dynamics.
Hanyang University IUCF’s 3D architecture portfolio is a licensable asset. The IUCF-HYU cluster (2015–2022) represents a focused 3D crossbar and selector IP portfolio that offers a potential licensing path for companies without deep internal research programs in 3D PCM integration. Partnerships or licensing arrangements with IUCF-HYU may offer a cost-effective route to 3D PCM IP.
Storage-class memory system IP has aged — creating white space. Several HGST filings from 2014–2016 are now inactive. This creates potential white space for new system architecture IP around PCM-based persistent memory in the context of CXL (Compute Express Link) memory architectures and AI server workloads — an area not yet well-represented in this dataset. Standards bodies including JEDEC are actively developing specifications for persistent memory interfaces that could define the next generation of storage-class memory system IP.
TSMC’s January 2026 CN patent filing describes a vertical PCRAM device integrating an oxide semiconductor transistor selector within the back-end metallization layers above the device layer, enabling embedded phase change memory in advanced logic process nodes without front-end process disruption.