Why copper interconnects are failing AI at scale

Copper-based electrical signal propagation is fundamentally constrained by resistance-capacitance time constants and electrical loss: as transmission speed and distance increase, the required conductor cross-section grows substantially, and signal crosstalk between channels limits both energy efficiency and bandwidth density. This is not a manufacturing problem — it is a physics problem, and it is documented explicitly across the patent dataset surveyed here, which encompasses more than 50 active and pending filings across Chinese, Korean, US, Taiwanese, and Japanese jurisdictions spanning roughly 2012 through early 2026.

The Hangzhou Guangzhiyuan Technology filing from 2025 quantifies the scaling wall precisely: leading electrical switch chips already require 5–7 nm process nodes and operate at 25.6–51.2 Tbps, and further scaling under Moore’s Law is severely constrained. The power overhead of optical-to-electrical-to-optical (OEO) conversion in existing optical module architectures adds cost and latency at each hop — a problem that becomes structurally worse as lane rates increase.

The photonic chiplet concept resolves this by integrating photonic integrated circuits (PICs) as disaggregated functional dies alongside electronic chiplets in advanced packaging. Rather than requiring a monolithic redesign of the entire chip, the chiplet-based architecture enables independent upgrade or replacement of photonic and electronic components while minimising packaging cost and improving yield by reducing individual die area — as documented in Shanghai Enflame Technology’s 2023 optical interconnect filings.

Optical interconnects offer what copper cannot: larger bandwidth, lower latency, lower power consumption, higher integration density, and stronger electromagnetic interference immunity. These are not marketing claims — they are the stated technical rationale appearing in filings from Shanghai Enflame, Zhejiang Laboratory, and Hangzhou Guangzhiyuan alike. According to IEEE, silicon photonics has been identified as one of the most promising integration paths for next-generation data centre connectivity, a view corroborated by the volume of filings now appearing from both US and Chinese assignees.

“Copper electrical interconnects cannot scale to meet the bandwidth and energy-efficiency demands of large-scale AI training and inference workloads — this is the overarching driver across virtually every filing in the dataset.”

Silicon photonic interposers: the core architectural primitive

The silicon photonic interposer is the most mature and widely patented photonic chiplet substrate concept in the dataset. It works by receiving continuous-wave (CW) optical signals, modulating them based on electrical signals from co-packaged electronic dies, and demodulating received optical signals back into electrical signals — a bidirectional electro-optical interface that distinguishes a photonic interposer from a passive optical substrate.

Luxtera established foundational claims in this space with filings from 2013 through 2020. Their 2013 filing establishes the complementary CMOS die-on-interposer architecture in which the silicon photonic interposer interfaces with standard CMOS electronic dies. Their 2014 hybrid integration filing specifies that Mach-Zehnder interferometric modulators can be used to process CW optical signals on the silicon photonic die, with the electronic die bonded via metal interconnects for ultra-short-reach electrical coupling. Luxtera was subsequently acquired by Cisco, anchoring these foundational patents within a major networking infrastructure vendor.

Lightmatter represents the most sophisticated current-generation photonic interposer architecture in the dataset. Their 2023 filing describes photonic interposers using programmable photonic tiles — each containing programmable photonic circuits — stitched together in 1D or 2D arrays to form a programmable physical network connecting pairs of tiles via photonic links. This architecture supports both board-level and rack-level inter-chip communication simultaneously, with low power and high bandwidth. Their 2025 filing extends this to a computing system comprising a photonic interposer with an optical network of waveguides and controllable optical switches, where an electronic die is surface-bonded to the interposer and exposed through internal and external electrical port interfaces — enabling both intra-chip and inter-chip optical routing within a single substrate.

Samsung Electronics has entered this space with a wafer-level approach: their 2024 filing proposes manufacturing silicon photonic packages at wafer level with an integrated optical source device, redistribution layers, and a solder bump array optimised for fibre optic array attachment. Taiwan Semiconductor Manufacturing Company’s 2025 filing takes a chip-stack approach, with each stack comprising a first photonic IC chip and a memory chip placed over it, connected through an optical interposer with optical waveguides — effectively enabling High-Bandwidth Memory (HBM)-style stacking with optical rather than electrical links.

Co-packaged optics, GPU clusters, and AI switch architectures

Three distinct application domains have emerged from the patent dataset, each with a different deployment timeline and technical priority: co-packaged optics for Ethernet switch ASICs (nearest-term), photonic chiplets for GPU-scale AI training cluster interconnects (mid-term), and photonic-linked disaggregated memory for AI inference (emerging).

Co-packaged optics for switch ASICs

The most commercially mature near-term deployment vector for photonic chiplets is co-packaged optics (CPO) for Ethernet switch chips. Inphi Corporation’s 2021 filing specifies a module substrate with a maximum lateral dimension of 110 mm, a central mounting site for the switch processor chip configured with a DSP interface for extra-short-reach (XSR) data interconnect, and multiple peripheral mounting sites for packaged light engine chiplets — each positioned within 50 mm of the main die to satisfy XSR electrical reach constraints. This is the architectural template that the OIF co-packaged optics multi-source agreement has subsequently standardised around, according to IEEE standards documentation.

Aya Labs’ 2023 filing proposes a network switch system-in-package in which a carrier substrate holds a network switch chip surrounded by photonic I/O modules. Each module contains a pod substrate with a photonic I/O chiplet and a gearbox chiplet. The photonic I/O chiplet implements a parallel electrical interface, an optical interface, and multiple optical macros, while the gearbox chiplet performs serialisation-to-parallel conversion between the photonic chiplet’s parallel interface and the switch chip’s serial electrical interface. This gearbox-photonic pod architecture decouples the optical modulation domain from the SerDes domain, allowing each to be optimised independently.

GPU-scale optical interconnects for AI training clusters

For AI training clusters requiring scale-up GPU interconnect (analogous to NVLink), photonic chiplets offer a fundamentally different value proposition: extending the reach and scale of GPU-to-GPU networks without the distance limitations of copper or the OEO overhead of pluggable modules. Suzhou Qidian Photonics Technology’s 2025 filing proposes packaging an optical chip, electronic chip, and microcontroller unit into a single OIO (Optical Input/Output) chiplet deployed on the scale-up network between GPUs. The patent claims that, compared to copper cable interconnect, the OIO chiplet significantly increases interconnect reach and thus the achievable scale-up network size; compared to existing optical module solutions, it offers lower latency, lower power consumption, higher bandwidth density, and higher reliability.

The Shanghai Shiao Communication Equipment 2025 filing addresses scale-out cluster limitations directly: it describes a GPU cluster topology problem in which an NVLink-style two-layer electrical switch network for 576 GPUs requires an exponentially growing count of switch chips and O/E modules with high cost and latency. The proposed hybrid solution introduces nanosecond-level optical switching at the core layer, with electrical switching only at the access layer — enabling larger GPU clusters without proportional growth in switch hardware cost. Shandong Cloud-Sea Innovation’s 2025 filing proposes a single-machine system combining electrical and optical switching matrices in a central hybrid switch chip, where control flow is routed through electrical links and data flow through optical links using wavelength-division multiplexing, with individual GPUs assigned distinct wavelength channels at 100 GHz spacing to avoid crosstalk. The filing claims 896 Gbps total bandwidth with collision-free transmission using this partitioned approach.

AI accelerator and memory integration

Celestial AI’s 2025 disaggregated memory architecture describes a computing system in which a compute circuit package and a memory circuit package are each built from co-integrated electronic and photonic ICs. Intra-chip bidirectional photonic channels connect processing element routers into an intra-chip network, while inter-chip bidirectional photonic channels connect the compute and memory packages across packages. Their 2024 electro-optical networks filing further specifies that each processing element includes a message router with a photonic channel interface, enabling packet-level optical messaging between processing elements — a critical feature for transformer workload bandwidth patterns. This architecture allows memory capacity to scale independently of compute, which is critical for large language model inference workloads.

Celestial AI’s 2026 Korean filing describes embedding a PIC die within a semiconductor package such that an optically transparent cavity allows optical signals to enter and exit through the package mould compound — enabling the PIC’s passive optical transmission medium to couple to external optical fibres while its active components interface electrically with co-packaged electronic ICs. This approach targets HBM-class bandwidth at memory bandwidth distances, a direction also pursued by TSMC in their 2025 chip-stack filing.

Key assignees and the shape of the patent landscape

Analysis of the dataset reveals three tiers of innovation activity, differentiated by geography, technical focus, and filing volume. The US-led Tier 1 established foundational architectures; a rapidly expanding Chinese ecosystem constitutes Tier 2; and Tier 3 covers memory and compute integration from a diverse set of assignees.

Tier 1 — Foundational Architecture (US/Global): Lightmatter is the most active photonic chiplet architecture company in the dataset, with at least four substantive filings. Their programmable photonic tile architecture is distinctive in enabling reconfigurable interconnect topology — a critical feature for AI workloads with varied collective communication patterns. Luxtera (acquired by Cisco) established the earliest silicon photonic interposer patents in the dataset, with filings from 2013 through 2020. Celestial AI appears with three substantive filings addressing both electro-optical networks for machine learning, disaggregated memory, and embedded PIC packaging. Inphi Corporation’s CPO co-packaging method (now Marvell) defines the switch-chip CPO package geometry that has become the reference architecture for next-generation 51.2T+ Ethernet switches.

Tier 2 — Chinese Ecosystem (Rapidly Expanding): Shanghai Enflame Technology holds multiple filings on optical interconnect devices, computing systems with 2D torus optical topology, and chips for optical interconnect modules — covering both chiplet-level photonic integration and system-level topology design. Hangzhou Guangzhiyuan Technology addresses all-optical on-chip switching networks. Xi’an University of Electronic Science and Technology’s 2024 filing proposes a novel die-to-die optical interconnect with active interposer CMOS control for routing reservation and fault recovery — demonstrating a strong academic-to-industrial pipeline. Huawei Technologies holds both AI switch chip architecture and optical network device patents, reflecting strategic investment across both the switch fabric and the optical module layers. The pace and breadth of Chinese filing activity is consistent with patterns documented by WIPO in its annual IP statistics, which have shown China as the largest filer of semiconductor-related patents since 2019.

Tier 3 — Memory/Compute Integration: Oracle International’s 2018 packaged optoelectronic module and 2015 chip assembly configuration filings represent earlier co-integration work establishing the optoelectronic module paradigm. D-Matrix Corporation’s 2023 generative AI accelerator and 2025 server system filings address the compute-memory bandwidth problem from the in-memory compute direction, using die-to-die interconnects to link chiplet devices within AI processing modules.

Emerging challenges: polarisation, fault tolerance, and disaggregated memory

Photonic chiplet systems are maturing from concept to productisation-readiness, and second-order engineering challenges are now appearing in the patent record — a reliable signal that the technology is approaching commercial deployment rather than remaining in the research phase.

Lightmatter’s 2025 polarisation rocker patent addresses polarisation drift in fibre-connected PICs. This is a practical reliability problem: single-mode fibres do not preserve polarisation state over distance or under mechanical stress, and silicon photonic modulators are typically polarisation-sensitive. Solving polarisation management at the fibre-PIC interface is a prerequisite for reliable high-volume deployment, and its appearance in the patent record confirms that Lightmatter is engineering for production rather than demonstration.

Xi’an University of Electronic Science and Technology’s 2024 electro-optical interleaved interconnect chip patent includes rerouting and fault-recovery mechanisms for optical link failures. This active interposer CMOS control for routing reservation and fault recovery addresses a fundamental reliability gap: optical waveguides and modulators can fail, and a production-grade photonic chiplet system must be able to detect and reroute around such failures without system-level downtime — a requirement familiar from electrical network fabric design but newly relevant in the photonic domain.

Celestial AI’s disaggregated memory architecture represents perhaps the most strategically significant emerging application. By connecting physically separated compute and memory packages via inter-chip bidirectional photonic channels, memory capacity can scale independently of compute — a capability that directly addresses the memory wall confronting large language model inference. The OECD has identified memory bandwidth as one of the primary bottlenecks to AI compute efficiency, and photonic disaggregated memory is the first credible architectural response to that constraint at scale.

The intelligent photonic GPU accelerator card from Intelligent Gene Networks Technology (Taiwan, 2025) integrates a photonic computing unit, photonic memory, WDM multiplexers/demultiplexers, electro-optic modulators, and photodetectors on a single accelerator card — with digital data converted to RF analogue signals through DACs to drive the electro-optic modulators for optical matrix computation, and results read back through photodetectors and ADCs. This direction, combining photonic computation with photonic interconnect, points toward a future in which the photonic chiplet is not merely a data transport element but an active compute participant — a trajectory that will significantly expand the scope of the patent landscape over the next filing cycle. For R&D teams tracking this space, the PatSnap R&D intelligence platform provides continuous monitoring of emerging assignee activity across all relevant jurisdictions.

“Polarisation management and fault tolerance are now appearing in the patent record — a reliable signal that photonic chiplet systems are transitioning from concept to productisation-readiness.”

Taken together, the dataset presents a technology in rapid transition. The foundational silicon photonic interposer architecture is established and licensed. Co-packaged optics for switch chips is approaching high-volume production. GPU-scale optical interconnects are being actively prototyped. Disaggregated memory with photonic links is in advanced concept development. And the second-order engineering challenges of polarisation management, fault recovery, and embedded PIC packaging are being addressed in real filings by real assignees — the clearest possible indicator that commercial deployment is no longer a distant prospect. Teams at PatSnap continue to monitor this landscape as new filings emerge across all five jurisdictions.