Why copper interconnects cannot scale for AI workloads

Copper-based electrical signal propagation is fundamentally constrained by resistance-capacitance time constants and electrical loss: as transmission speed and distance increase, the required conductor cross-section grows substantially, and signal crosstalk between channels limits both energy efficiency and bandwidth density. This is not a manufacturing problem that can be engineered away — it is a physics constraint that becomes increasingly acute as AI training clusters demand higher aggregate bandwidth between GPUs, switches, and memory.

The dataset of more than 50 active and pending filings surveyed here — spanning Chinese, Korean, US, Taiwanese, and Japanese jurisdictions from roughly 2012 through early 2026 — converges on the same diagnosis. A 2025 patent from Hangzhou Guangzhiyuan Technology quantifies the ceiling: leading electrical switch chips already require 5–7 nm process nodes and operate at 25.6–51.2 Tbps, and further scaling under Moore’s Law is severely constrained. The power overhead of optical-to-electrical-to-optical (OEO) conversion in existing pluggable optical module architectures adds cost and latency at every hop. A 2026 filing from Zhejiang Laboratory cites Google‘s Jupiter all-optical switching deployment as evidence that eliminating OEO conversion in the switching fabric can dramatically reduce power and latency — but notes that pluggable optical modules on the server side remain a bandwidth and power bottleneck as lane rates increase.

The photonic chiplet concept — integrating photonic integrated circuits (PICs) as disaggregated functional dies alongside electronic chiplets in advanced packaging — is the proposed resolution. Rather than requiring a monolithic redesign of the entire chip, photonic chiplets allow modular upgrades: a chiplet-based architecture enables independent upgrade or replacement of photonic and electronic components while minimising packaging cost and improving yield by reducing individual die area, as documented in a 2023 filing from Shanghai Enflame Technology.

Silicon photonic interposers: the core architectural primitive

The silicon photonic interposer is the most mature and widely patented photonic chiplet substrate concept in the dataset, operating by receiving continuous-wave (CW) optical signals, modulating them based on electrical signals from co-packaged electronic dies, and demodulating received optical signals back into electrical signals — a bidirectional electro-optical interface that distinguishes a photonic interposer from a passive optical substrate. Luxtera established foundational claims in this space as early as 2013, with filings covering complementary CMOS die-on-interposer architecture and Mach-Zehnder interferometric modulators for CW optical signal processing, with the electronic die bonded via metal interconnects for ultra-short-reach electrical coupling.

Lightmatter represents the most sophisticated current-generation photonic interposer architecture in the dataset. Their 2023 Photonic Communication Platform describes photonic interposers that use programmable photonic tiles — each containing programmable photonic circuits — stitched together in 1D or 2D arrays to form a programmable physical network connecting pairs of tiles via photonic links. This architecture supports both board-level and rack-level inter-chip communication simultaneously, with low power and high bandwidth. Their 2025 Chiplet Communication Using Optical Communication Substrates filing further discloses a computing system comprising a photonic interposer with an optical network of waveguides and controllable optical switches, where an electronic die is surface-bonded to the interposer and exposed through internal and external electrical port interfaces — enabling both intra-chip and inter-chip optical routing within a single substrate.

“Photonic chiplets allow modular upgrades: independent upgrade or replacement of photonic and electronic components while minimising packaging cost and improving yield by reducing individual die area.”

Celestial AI extends the interposer paradigm to disaggregated memory. Their 2025 Disaggregated Memory Architecture describes a computing system in which a compute circuit package and a memory circuit package are each built from co-integrated electronic and photonic ICs; intra-chip bidirectional photonic channels connect processing element routers into an intra-chip network, while inter-chip bidirectional photonic channels connect the compute and memory packages across packages. Their 2024 Electro-Optical Networks for Machine Learning filing further specifies that each processing element includes a message router with a photonic channel interface, enabling packet-level optical messaging between processing elements — a critical feature for transformer workload bandwidth patterns.

Taiwan Semiconductor Manufacturing Company’s 2025 Integrated Memory Device with Optical Link takes a chip-stack approach, with each stack comprising a first photonic IC chip and a memory chip placed over it, connected through an optical interposer with optical waveguides — effectively enabling High-Bandwidth Memory (HBM)-style stacking with optical rather than electrical links. Samsung Electronics has simultaneously entered this space with a wafer-level approach: their 2024 Silicon Photonics Package and Switch Package proposes manufacturing silicon photonic packages at wafer level with an integrated optical source device, redistribution layers, and a solder bump array optimised for fiber optic array attachment. Standards bodies including IEEE and industry consortia such as the OIF have been active in defining the interoperability frameworks that will govern multi-vendor photonic chiplet deployments.

Co-packaged optics, GPU clusters, and AI switch architectures

Photonic chiplets address three distinct deployment contexts in AI data centers, each with different packaging constraints, bandwidth requirements, and competitive dynamics: co-packaged optics for switch ASICs, scale-up GPU interconnects for training clusters, and AI accelerator memory integration for inference.

Co-packaged optics for switch ASICs

The most commercially mature near-term deployment vector for photonic chiplets is co-packaged optics (CPO) for Ethernet switch chips. Inphi Corporation’s 2021 Method for Co-Packaging Light Engine Chiplets on Switch Substrate specifies a module substrate with a maximum lateral dimension of 110 mm, a central mounting site for the switch processor chip configured with a DSP interface for extra-short-reach (XSR) data interconnect, and multiple peripheral mounting sites for packaged light engine chiplets — each positioned within 50 mm of the main die to satisfy XSR electrical reach constraints. This is the architectural template that the OIF co-packaged optics multi-source agreement has subsequently standardised around, targeting the 51.2T+ Ethernet switch generation.

Aya Labs’ 2023 Low-Power Optical Input/Output Chiplet for Ethernet Switches proposes a network switch system-in-package in which a carrier substrate holds a network switch chip surrounded by photonic I/O modules; each module contains a pod substrate with a photonic I/O chiplet and a gearbox chiplet. The gearbox chiplet performs serialisation-to-parallel conversion between the photonic chiplet’s parallel interface and the switch chip’s serial electrical interface — decoupling the optical modulation domain from the SerDes domain so each can be optimised independently. Research published by organisations including Nature has documented the photonics integration challenges that make this gearbox architecture necessary at high lane rates.

GPU-scale optical interconnects for AI training clusters

For AI training clusters requiring scale-up GPU interconnect (analogous to NVLink), photonic chiplets offer a fundamentally different value proposition: extending the reach and scale of GPU-to-GPU networks without the distance limitations of copper or the OEO overhead of pluggable modules. Suzhou Qidian Photonics Technology’s 2025 OIO Chiplet and AI Computing Cluster patent proposes packaging an optical chip, electronic chip, and microcontroller unit into a single OIO (Optical Input/Output) chiplet deployed on the scale-up network between GPUs — designed to be co-located with the GPU on the same PCB or co-packaged on the same substrate. The patent claims that, compared to copper cable interconnect, the OIO chiplet significantly increases interconnect reach and thus the achievable scale-up network size; compared to existing optical module solutions, it offers lower latency, lower power consumption, higher bandwidth density, and higher reliability.

The GPU-Interconnect High-Speed Electro-Optical Switching Network from Shanghai Shiao Communication Equipment (2025) addresses scale-out cluster limitations: it describes a GPU cluster topology problem in which an NVLink-style two-layer electrical switch network for 576 GPUs requires an exponentially growing count of switch chips and O/E modules with high cost and latency. The proposed hybrid solution introduces nanosecond-level optical switching at the core layer, with electrical switching only at the access layer — enabling larger GPU clusters without proportional growth in switch hardware cost.

Shandong Cloud-Sea Innovation’s 2025 GPU Communication Method Using Electro-Optical Hybrid Switch proposes a single-machine system combining electrical and optical switching matrices in a central hybrid switch chip, where control flow is routed through electrical links and data flow through optical links using wavelength-division multiplexing — with individual GPUs assigned distinct wavelength channels (λ1–λ8 at 100 GHz spacing) to avoid crosstalk. The filing claims 896 Gbps total bandwidth with collision-free transmission using this partitioned approach.

AI accelerator and memory integration

Celestial AI’s 2026 Embedding Photonic Integrated Circuits Within Semiconductor Packages for High-Bandwidth Memory and Computing describes embedding a PIC die within a semiconductor package such that an optically transparent cavity allows optical signals to enter and exit through the package mold compound — enabling the PIC’s passive optical transmission medium to couple to external optical fibers while its active components interface electrically with co-packaged electronic ICs. This approach targets HBM-class bandwidth at memory bandwidth distances. The Photonic AI GPU Accelerator Card from Intelligent Gene Networks Technology (Taiwan, 2025) integrates a photonic computing unit, photonic memory, WDM multiplexers/demultiplexers, electro-optic modulators, and photodetectors on a single accelerator card, with digital data converted to RF analog signals through DACs to drive the electro-optic modulators for optical matrix computation, and results read back through photodetectors and ADCs.

Leading assignees and the competitive patent landscape

Analysis of the dataset reveals three tiers of innovation activity, differentiated by filing volume, technical scope, and jurisdictional reach — with a notable and accelerating expansion of Chinese assignee activity from 2023 onwards.

Lightmatter is the most active photonic chiplet architecture company in the dataset, with at least four substantive filings: the 2023 Photonic Communication Platform (US), the 2024 Korean counterpart, the 2025 Chiplet Communication Using Optical Communication Substrates, and a 2025 Polarizing Rockers for Fiber Connections filing addressing polarisation management in photonic interconnect systems. Their programmable photonic tile architecture is distinctive in enabling reconfigurable interconnect topology — a critical feature for AI workloads with varied collective communication patterns.

Luxtera (acquired by Cisco) established the earliest silicon photonic interposer patents in the dataset, with filings from 2013 through 2020 covering both photonic interposer methodology and hybrid integration of optical communication systems. Celestial AI appears with three substantive filings addressing electro-optical networks for ML (2024 Korean filing), disaggregated memory (2025 US filing), and embedded PIC packaging (2026 Korean filing). Inphi Corporation’s CPO co-packaging method (2021, now Marvell) defines the switch-chip CPO package geometry that has become the reference architecture for next-generation 51.2T+ Ethernet switches.

The Chinese ecosystem represents the fastest-growing patent activity cohort. Shanghai Enflame Technology holds multiple filings on optical interconnect devices, computing systems with 2D torus optical topology, and chips for optical interconnect modules — covering both chiplet-level photonic integration and system-level topology design. Hangzhou Guangzhiyuan Technology addresses all-optical on-chip switching networks, while Zhejiang Laboratory’s 2026 filing cites Google’s Jupiter deployment as a reference point. Xi’an University of Electronic Science and Technology’s 2024 electro-optical interleaved interconnect chip for advanced packaging demonstrates strong academic-to-industrial pipeline activity, proposing a novel die-to-die optical interconnect with active interposer CMOS control for routing reservation and fault recovery. Huawei Technologies holds both AI switch chip architecture and optical network device patents, reflecting its strategic investment across both the switch fabric and the optical module layers. Intellectual property organisations including WIPO have tracked the rapid internationalisation of photonic chiplet filings across these jurisdictions.

Emerging second-order challenges: polarisation management and fault tolerance

As photonic chiplet architectures move from concept to productisation-readiness, a second generation of technical challenges is surfacing in the patent record — challenges that signal the technology is maturing toward commercial deployment rather than remaining at the research stage.

Lightmatter’s 2025 Polarizing Rockers for Fiber Connections patent addresses polarisation drift in fiber-connected PICs — a reliability concern that arises when photonic chiplets are connected to external fibers in real-world data center environments where mechanical vibration, temperature cycling, and cable routing all introduce polarisation state changes that can degrade signal fidelity. The existence of a dedicated polarisation management filing indicates that Lightmatter’s photonic interposer platform has advanced to the point where fiber connection reliability is an active engineering problem, not a theoretical one.

Xi’an University of Electronic Science and Technology’s 2024 electro-optical interleaved interconnect chip includes rerouting and fault-recovery mechanisms for optical link failures — with active interposer CMOS control managing routing reservation and fault recovery across the die-to-die optical interconnect. This fault-recovery capability is a prerequisite for deploying photonic chiplets in production AI training clusters, where a single interconnect failure in a 576-GPU fabric would otherwise require a full cluster restart. The IEEE has published reliability standards relevant to optical interconnect systems that will inform how these fault-tolerance mechanisms are evaluated in production environments.

Together, these second-order filings — polarisation management, fault recovery, routing reservation — indicate that the photonic chiplet field has crossed a maturity threshold. The primary technical question is no longer whether photonic chiplets can deliver higher bandwidth and lower power than copper interconnects; the dataset establishes that they can. The questions now being answered in patents are how to make photonic chiplet systems reliable, manufacturable at scale, and interoperable across multi-vendor data center environments — the same questions that determined the commercial trajectory of every previous generation of data center interconnect technology. Patent databases maintained by authorities including EPO and USPTO continue to be the primary public record of this maturation process.

“The primary question is no longer whether photonic chiplets can deliver higher bandwidth and lower power than copper. The questions now being answered in patents are how to make them reliable, manufacturable at scale, and interoperable across multi-vendor environments.”