What PIC packaging is and why it is uniquely complex

A photonic integrated circuit (PIC) is a semiconductor die that integrates optical and optoelectronic functions — waveguides, modulators, photodetectors, and sometimes lasers — onto a single chip. Packaging that chip means mechanically housing it, electrically coupling its active components to an electronic integrated circuit (EIC), and simultaneously providing optical access so that light can enter and exit the package from optical fibers or free-space sources. This dual requirement — electrical density combined with precise optical coupling — is what makes PIC packaging fundamentally more complex than conventional semiconductor packaging.

The structural anatomy of a PIC package is defined by two distinct regions on the die itself. As described in Celestial AI Inc.’s 2025 US patent, the PIC comprises an active portion — consuming electrical power and driving electro-optic components — and a passive portion, an optical transmission medium that propagates optical signals. The EIC is electrically coupled to the active portion, while a packaging compound encapsulates the assembly and defines a cavity filled with an optically transparent medium above the passive optical ports. Without this transparent-cavity architecture, conventional opaque molding compounds would block optical access entirely.

The challenge of maintaining optical access throughout the manufacturing flow is addressed by Celestial AI’s 2026 Korean patent on fabrication of optically accessible co-packaged optical devices, which introduces sacrificial spacers placed over the PIC at different fabrication stages to preserve the optical path during molding. These spacers are added and later removed at successive process steps, ensuring the cavity remains optically clear in the final package — directly addressing a key yield challenge in PIC packaging manufacturing. Samsung Electronics takes a complementary approach in its 2026 Korean patent, where an optical engine unit comprising a stacked PIC chip and EIC chip is mounted on an intermediate substrate, topped with a transparent support layer above the EIC, and co-integrated alongside a logic element and memory element to realise a complete compute-optical-memory assembly in one package.

The three dominant packaging architectures

Three distinct structural approaches have emerged from the patent record to solve the PIC packaging challenge: cavity-based embedding within interposers or substrates, fan-out redistribution layer (RDL) and mold-based system-in-package (SiP) architectures, and 3D die-on-die stacking with optical bridges. Each trades off manufacturability, interconnect density, and optical coupling flexibility differently.

Cavity-based embedding and interposer approaches

Intel’s dominant approach leverages cavities in the package substrate or interposer to house PICs at the same z-height as other dies, minimising the electrical interconnect distance. In Intel’s 2025 Netherlands patent, the interposer contains a cavity proximate to its conductive contacts, and those contacts couple directly to the PIC’s conductive pads — enabling a seamless electrical interface without long wire bonds. Intel’s 2023 US patent extends this to multi-chip integration, placing a photonic integrated circuit cavity bridge (PIC-CB) inside the substrate cavity, with EICs above and electrically coupled to both the bridge and the PIC, supporting high-density routing across multiple embedded bridges simultaneously.

Fan-out RDL and redistribution layer architectures

Fan-out wafer-level packaging (FOWLP) with redistribution layers (RDL) has emerged as the most manufacturable approach for co-integrating PICs and EICs at scale. Intel’s 2025 European patent describes using a fan-out redistribution layer (FORDL) to extend the reach of a PIC’s electrical connectors to an Embedded Multi-Die Interconnect Bridge (EMIB), which then couples to a CPU, GPU, or FPGA. This scheme resolves the geometric mismatch between a PIC die’s relatively large optical aperture region and the fine-pitch electrical pads required by modern processors — a problem that has no direct analog in all-electronic packaging.

AMD’s 2022 US patent builds a dual-mold RDL structure: the first mold layer encases the PIC; an RDL is built on top providing electrical pathways; and a second mold layer encases the semiconductor chips placed on the RDL above. Voids are defined in the upper mold layer directly above the PIC’s optical interface to preserve light transmission. Korean company Raipac’s Optical System-in-Package (O-SIP) family adopts a similar principle, co-molding a photonic IC and an electronic IC inside a single mold body with a vertical coupler through-hole above the PIC’s optical port to accommodate fiber attachment. Samsung Electro-Mechanics contributes substrate-level embedding via its 2024 US patent, where the PIC is embedded in an insulating layer and the stack above it incorporates an optical path extending in the stacking direction — meaning the package substrate itself contains a vertical optical channel aligned to the PIC’s grating couplers.

3D stacking and die-on-die integration

Celestial AI’s core packaging IP revolves around tightly stacked PIC/EIC assemblies with precision copper pillar interconnects. In its 2025 US patent on electrical interconnects for packages containing photonic integrated circuits, the EIC is stacked directly on the PIC, with copper pillars protruding from the EIC’s landing pads and connecting to the active photonic components on the PIC below. A crucial design constraint is specified: when viewed from EIC toward PIC, the active photonic component is laterally offset from the landing pad centre — this offset is engineered to limit parasitic capacitance between the metal landing pad and the photonic device to within a predetermined tolerance threshold, preventing RF degradation. This constraint has no direct analog in conventional all-electronic stacking.

Intel discloses vertical stacking of multiple PIC dies in its 2025 Chinese patent on technologies for stacked photonic integrated circuit dies, where two or more PIC dies are stacked with an EIC die on top, and optical coupling between the stacked PIC layers is achieved via reflectors in an optical bridge, direct-write waveguides, or photonic wire bonding. The document explicitly notes that stacking increases yield, reduces footprint, and allows different PIC technology nodes to be combined in a single device. Lightmatter’s 2025 Korean patent takes a photonic interposer approach in which the interposer itself hosts a full optical network of waveguides and controllable optical switches, with electronic chiplets bonded face-down onto the photonic interposer surface.

“Stacking multiple PIC dies with optical bridges addresses a fundamental yield problem: as PIC die sizes grow to support more channels, yield per die drops. Smaller, higher-yield PIC tiles can be optically coupled and assembled into a larger effective PIC — reducing cost and enabling multi-technology integration within the same package.”

Optical fiber coupling: the hardest step in the process

Optical coupling to external fibers is the highest-cost and lowest-yield step in PIC packaging, and the field has produced several distinct approaches to address it. While electrical interconnects between PIC and EIC can leverage established flip-chip or wire-bond methodologies with modifications, fiber attachment requires sub-micron alignment tolerances that no standard semiconductor assembly tool can achieve without specialised hardware or passive alignment features.

Intel’s 2025 US patent on photonic integrated circuit packaging architecture couples optical lenses to the lateral sides of the PIC — perpendicular to the active surface — enabling edge-coupled fiber attachment while the active side faces the package substrate for electrical connection. Intel’s 2023 German patent (filed by GlobalFoundries) addresses high-density edge coupling through optical interconnect slots in the PIC die that align fiber cores to on-chip waveguides at different vertical and lateral depths within the die body. Multiple slot depths allow multiple fiber arrays to connect to different layers within the same PIC die simultaneously, dramatically increasing fiber density per chip edge without inter-channel crosstalk.

Intel’s 2025 US patent on expanded beam connectors introduces a detachable expanded beam connector — a second optical element that expands and collimates the beam from the fiber, placed between the fiber array and the PIC’s on-chip optical element. The connector body can be fabricated from 3D-printed optical polymer, 3D-printed glass, fused silica, or optical-grade resin, enabling field-removable fiber arrays without the permanent adhesive bonds that complicate repair and rework in deployed data center hardware. This is a significant operational advantage: in a live data center, the ability to replace a fiber array without desoldering or re-bonding the package can reduce maintenance downtime substantially.

Luxtera (now part of Cisco) pioneered a complementary approach via silicon photonic interposers, where a silicon photonic interposer receives continuous-wave (CW) optical signals from external fibers via grating couplers, processes them based on electrical signals from attached CMOS dies, and transmits electrical output signals via copper pillars to those dies. This architecture separates the optical coupling function — handled by the silicon photonic layer — from the computation function handled by conventional CMOS, enabling independent optimisation of each. Eindhoven University of Technology’s multi-port optical probe work demonstrates passive optical alignment using flexible waveguide elements in an interposer unit, with dedicated alignment features for lateral, vertical, and longitudinal passive self-alignment of flexible waveguide tips to on-chip waveguides — a technique directly relevant to high-volume automated assembly where active alignment is too slow or costly.

Co-packaged optics and the data center bandwidth wall

The fundamental motivation for PIC packaging in data centers is the impending collapse of electrical I/O scaling. Future-generation processors require optical interconnects to achieve the required compute density and I/O bandwidth because conventional electrical solutions suffer from high signal loss at increasing data rates. As noted in Intel’s Chinese patent on co-packaging of photonic and electronic integrated circuit dies, as ASIC processing speeds increase, an I/O system with insufficient optical bandwidth becomes the performance bottleneck preventing the ASIC from operating at its full capability.

The Intel EMIB/FORDL architecture for CPUs and PICs was explicitly motivated by the need for processors to achieve terabits-per-second I/O bandwidth over distances exceeding 100 metres, as articulated in Intel’s Japanese counterpart patent from 2022. Google addresses this at the system level via its ASIC packaging approach, where one or more photonic modules — each incorporating a PIC and a fiber array — are attached to the package substrate, with SerDes interfaces connecting the ASIC die to each photonic module. Google’s integration work for silicon photonic ICs identified wire bonding as introducing parasitic inductance that limits scalability for high data rates, proposing vertical flip-chip integration and horizontal tiling on chip carriers as solutions that minimise RF loss and enable cost-effective large-volume manufacturing.

High-bandwidth memory and AI compute packaging

Celestial AI’s portfolio is specifically oriented toward PIC packaging for AI accelerator and high-bandwidth memory (HBM) systems. Its core WO 2025 patent describes the transparent-cavity molded package that enables optical signals to traverse through the encapsulant, bridging the PIC’s passive waveguide layer to external optical interconnects — enabling high-bandwidth photonic data transmission between HBM stacks and AI processor dies within a single package. According to IEEE publications on photonic integration, the bandwidth density achievable through co-packaged silicon photonics exceeds what is achievable with copper-based SerDes at comparable power envelopes, making photonic I/O essential for next-generation AI training clusters.

Nubis Communications targets wafer-scale AI processors by deploying arrays of PICs near the edges of wafer-scale processing modules. Each optical I/O module converts optical signals from external links to electrical signals for the processor array, and converts outbound electrical signals back to optical for transmission. Signal propagation loss on the wafer-level connections is explicitly managed through path length minimisation. Lightmatter’s WO 2022 patent applies PIC packaging to photonic matrix multiplication for AI inference acceleration: multiple PICs, each implementing a photonic accelerator performing matrix operations in the optical domain, are coupled to one side of an interposer while an ASIC controller is attached to the opposite side, with dedicated heat spreaders for the PICs and a separate lid for the ASIC recognising that PIC and EIC thermal profiles differ substantially.

Data center switching fabric

Huawei/Futurewei’s WO 2015 patent deploys silicon photonic PIC switches within data center fabric architectures, using compact silicon photonic circuits arranged in both centralised and distributed configurations, with NxN SiP optical switch matrices at each rack group and 1xP SiP switches providing paths to core photonic switches. This all-photonic switching fabric eliminates electrical-to-optical conversion at intermediate switching nodes, directly reducing latency and power per bit in the data center spine-leaf topology. TSMC’s co-packaged switching approach integrates a photonic die, an electronic die, and a switch ASIC within a single interconnect package, with SerDes circuits, transceivers, clocking circuits, and control logic from the electronic die integrated directly into the switch ASIC — eliminating the pluggable optics module entirely. Standards bodies including IEEE and industry groups tracked by WIPO have identified co-packaged optics as a critical technology for 800G and 1.6T Ethernet data center switching.

Key players and the global patent landscape

Intel Corporation is the single most prolific PIC packaging assignee, with filings across US, WO, EP, KR, CN, NL, and JP jurisdictions covering cavity-based PIC embedding, interposer-mounted PICs, EMIB/FORDL co-packaging, stacked PIC dies, V-groove fiber attachment, expanded-beam detachable connectors, and glass-substrate multi-die packages. Intel’s breadth suggests a platform approach — developing multiple interchangeable packaging architectures rather than a single proprietary solution.

Celestial AI Inc. holds a tightly focused portfolio around transparent-cavity molded PIC packaging and precision copper-pillar EIC-on-PIC stacking, with filings in US, WO, KR, and CN directly addressing the HBM and AI accelerator market. Samsung Electronics and Samsung Electro-Mechanics contribute substrate-embedded PIC technology and full optical engine unit packaging, targeting memory-integrated photonic packages positioned for next-generation HBM modules with integrated photonic I/O. Raipac Co., Ltd. (Korea) has built a coherent O-SIP product family covering optical modules, transceivers, and system-in-package configurations, with focus on laser diode integration into the molded package alongside PIC and EIC. AMD contributes the dual-mold fan-out RDL module architecture directly relevant to integrating PICs with AMD’s CPU and GPU chiplet ecosystem. Lightmatter occupies a distinct niche as a photonic AI compute company, with its photonic interposer and matrix-multiplication PIC packages documented across WO and KR filings.

An important geographic trend from the dataset: significant Korean and Chinese patent activity from Samsung, Raipac, and Celestial AI’s CN filings appears alongside US and European filings, indicating that PIC packaging has become a globally contested technology domain — not merely a Western semiconductor story. According to WIPO‘s technology trend tracking, photonic integrated circuits are among the fastest-growing semiconductor patent categories globally, with the concentration of recent filings from 2022 to 2026 reflecting a sharp acceleration driven by exponential data center bandwidth demands. The PatSnap R&D intelligence platform enables teams to track this evolving competitive landscape across all 11 active jurisdictions in real time.

“The concentration of recent filings from 2022 to 2026 reflects a sharp acceleration in PIC packaging innovation driven by exponential data center bandwidth demands — with Intel, Celestial AI, Samsung, and Raipac all filing across multiple jurisdictions simultaneously.”

Google and Huawei/Futurewei represent the hyperscaler and networking equipment perspectives respectively, each deploying PIC packaging at the system integration level for data center switching and AI ASIC packaging. TSMC’s involvement — integrating photonic die, electronic die, and switch ASIC within a single interconnect package — signals that foundry-level co-packaged optics manufacturing has moved from research to production readiness. For R&D teams tracking freedom-to-operate or competitive positioning in this space, the PatSnap patent analytics platform provides structured access to the full filing history across all assignees and jurisdictions covered in this analysis.