What PIC packaging is and why it is uniquely difficult
A photonic integrated circuit (PIC) is a semiconductor die that integrates optical and optoelectronic functions — waveguides, modulators, photodetectors, and sometimes lasers — onto a single chip. Packaging a PIC means mechanically housing it, electrically coupling its active components to an electronic integrated circuit (EIC), and simultaneously providing optical access so that light can enter and exit the package from optical fibers or free-space sources. This dual requirement — electrical density combined with precise optical coupling — is what makes PIC packaging fundamentally more complex than conventional semiconductor packaging.
The structural anatomy of a PIC package is well-captured in Celestial AI Inc.’s 2025 US patent on embedding a PIC in a semiconductor package for high-bandwidth memory and compute. The patent defines a PIC as comprising an active portion — consuming electrical power and driving electro-optic components — and a passive portion, which is an optical transmission medium propagating optical signals. The EIC is electrically coupled to the active portion, while a packaging compound encapsulates the assembly and defines a cavity filled with an optically transparent medium above the passive optical ports, enabling light to pass through the top surface of the package.
Conventional opaque molding compounds used in standard semiconductor packaging would block all optical access to the PIC’s waveguide ports. Transparent-cavity approaches — where a clear medium is defined above the passive optical region — are therefore a foundational requirement, not an optional feature, in any PIC package design.
The challenge of maintaining optical access throughout the manufacturing flow is addressed by Celestial AI’s 2026 Korean patent on fabricating optically accessible co-packaged optical devices, which introduces sacrificial spacers placed over the PIC at different fabrication stages to preserve the optical path during molding. Different spacers are added and later removed at successive process steps, ensuring the cavity remains optically clear in the final package — directly addressing a key yield challenge in PIC packaging manufacturing.
PIC packaging requires simultaneously achieving high-density electrical connections to the active photonic components and providing an unobstructed optical path through or around the packaging compound to the passive waveguide ports — a dual requirement with no direct analogue in conventional electronic semiconductor packaging.
Samsung Electronics takes a complementary structural approach in its 2026 Korean semiconductor package patent, where an optical engine unit comprising a stacked PIC chip and EIC chip is mounted on an intermediate substrate, surrounded by multiple insulating layers, and topped with a transparent support layer above the EIC to maintain the optical path. This is co-integrated on the same intermediate substrate alongside a logic element and memory element, realising a complete compute-optical-memory assembly in one package.
Packaging architectures: cavity embedding, RDL fan-out, and 3D stacking
Three dominant technical approaches have emerged from the patent literature, each making different trade-offs between integration density, manufacturability, and optical access: cavity-based embedding within interposers or substrates; fan-out redistribution layer (RDL) and mold-based system-in-package (SiP) architectures; and 3D die-on-die stacking with precision copper-pillar interconnects.
Cavity-based embedding and interposer approaches
Intel’s dominant approach leverages cavities in the package substrate or interposer to house PICs at the same z-height as other dies, minimising the electrical interconnect distance. In its 2025 Netherlands patent on a photonic integrated circuit within a cavity of interposer, the interposer contains a cavity proximate to its conductive contacts, and those contacts couple directly to the PIC’s conductive pads — enabling a seamless electrical interface without long wire bonds. The PIC resides recessed within the interposer cavity at the correct height for face-to-face contact with an EIC mounted above it.
Intel’s 2023 US patent on photonics packaging with high-density routing extends this concept to multi-chip integration, placing a photonic integrated circuit cavity bridge (PIC-CB) inside the substrate cavity, with EICs above and electrically coupled to both the bridge and the PIC. In a separate 2025 Korean patent on embedded photonic integrated circuits, the substrate for a multi-chip package includes one or more PIC interposers mounted within cavities on its principal surface, each capable of being electrically or optically coupled to multiple IC devices, with at least one optical coupler also embedded in the substrate to route light between dies.
Fan-out RDL and redistribution layer architectures
Fan-out wafer-level packaging (FOWLP) with redistribution layers has emerged as the most manufacturable approach for co-integrating PICs and EICs at scale. Intel’s 2025 EP patent on an integrated photonics and processor package describes using a fan-out redistribution layer (FORDL) to extend the reach of a PIC’s electrical connectors to an Embedded Multi-Die Interconnect Bridge (EMIB), which then couples to a CPU, GPU, or FPGA. This scheme resolves the geometric mismatch between a PIC die’s relatively large optical aperture region and the fine-pitch electrical pads required by modern processors.
AMD’s 2022 US patent on a fanout module integrating a photonic integrated circuit builds a dual-mold RDL structure: the first mold layer encases the PIC; an RDL is built on top providing electrical pathways; and a second mold layer encases the semiconductor chips placed on the RDL above. Voids are defined in the upper mold layer directly above the PIC’s optical interface to preserve light transmission through the dielectric. Korean company Raipac’s Optical System-in-Package (O-SIP) family adopts a similar principle, co-molding a photonic IC and an electronic IC inside a single mold body with bonding pads exposed on the upper surface, and a redistribution layer with fan-out terminal pads interconnecting them.
Samsung Electro-Mechanics contributes substrate-level embedding via its 2024 US patent on a photonic integrated circuit embedded substrate, where the PIC is embedded in an insulating layer and the stack above it includes at least one additional insulating layer with an optical path extending in the stacking direction — meaning the package substrate itself incorporates a vertical optical channel aligned to the PIC’s grating couplers or surface optical ports.
3D stacking and die-on-die integration
Celestial AI’s core packaging IP revolves around tightly stacked PIC/EIC assemblies with precision copper pillar interconnects. In its 2025 US patent on electrical interconnects for packages containing photonic integrated circuits, the EIC is stacked directly on the PIC, with copper pillars protruding from the EIC’s landing pads and connecting to the active photonic components on the PIC below. A crucial design constraint is specified: when viewed from EIC toward PIC, the active photonic component is laterally offset from the landing pad centre — this offset is engineered to limit parasitic capacitance between the metal landing pad and the photonic device to within a predetermined tolerance threshold, preventing RF degradation.
Celestial AI’s copper pillar architecture explicitly offsets active photonic components laterally from EIC landing pads to keep parasitic capacitance within tolerance, preventing RF signal degradation. This is a design constraint unique to photonic packages with no direct analogue in conventional electronic stacking — and one that directly limits how densely PIC and EIC components can be co-located.
Intel’s 2025 Chinese patent on technologies for stacked photonic integrated circuit dies discloses vertical stacking of multiple PIC dies, where two or more PIC dies are stacked with an EIC die on top, and optical coupling between the stacked PIC layers is achieved via reflectors in an optical bridge, direct-write waveguides, or photonic wire bonding. The document explicitly notes that stacking increases yield, reduces footprint, and allows different PIC technology nodes to be combined in a single device — addressing the well-known yield scaling problem for large-area PICs.
Explore the full PIC packaging patent landscape across all jurisdictions with PatSnap Eureka.
Analyse PIC Patents in PatSnap Eureka →Fan-out wafer-level packaging (FOWLP) with redistribution layers (RDL) has emerged as the most manufacturable approach for co-integrating photonic ICs and electronic ICs at scale, enabling photonic IC and electronic IC co-molding with fan-out terminal pads in a structure compatible with standard wafer-level packaging lines.
Lightmatter’s 2025 Korean patent on chiplet communication using optical communication substrates takes a photonic interposer approach in which the interposer itself hosts a full optical network of waveguides and controllable optical switches, with electronic chiplets bonded face-down onto the photonic interposer surface. The internal interface — coupling power and data between the die and interposer — is surrounded by an external interface, creating a structured port arrangement that enables chip-to-chip optical communication without external fibers between chiplets.
Optical fiber coupling: the highest-cost, lowest-yield step
Fiber attachment is the highest-cost and lowest-yield step in PIC packaging, requiring precise alignment of fiber cores to on-chip waveguides at sub-micron tolerances. While electrical interconnects between PIC and EIC can leverage established flip-chip or wire-bond methodologies with modifications, optical coupling to external fibers remains the most technically demanding challenge — and the field has produced several distinct approaches to address it.
“Fiber attachment remains the highest-cost and lowest-yield step, motivating diverse mechanical approaches including V-groove slots, expanded-beam detachable connectors, and multi-depth multi-stage fiber slots for high-density arrays.”
Intel’s 2025 US patent on a photonic integrated circuit packaging architecture couples optical lenses to the lateral sides of the PIC — perpendicular to the active surface — enabling edge-coupled fiber attachment while the active side faces the package substrate for electrical connection. An insulating material fills most of the active side’s surrounding area, with optical structures on the active side for electro-optic device access, and the interposer or package support provides the vertical electrical path.
A GlobalFoundries 2023 German patent on PIC die and package with multi-stage connections addresses high-density edge coupling, where optical interconnect slots in the PIC die align fiber cores to on-chip waveguides at different vertical and lateral depths within the die body. Multiple slot depths allow multiple fiber arrays to connect to different layers within the same PIC die simultaneously, dramatically increasing fiber density per chip edge without inter-channel crosstalk.
Intel’s 2025 US patent on photonic integrated circuit packages including an on-package expanded beam connector introduces a detachable expanded beam connector — a second optical element that expands and collimates the beam from the fiber, placed between the fiber array and the PIC’s on-chip optical element. The connector body can be fabricated from 3D-printed optical polymer, 3D-printed glass, fused silica, or optical-grade resin, enabling field-removable fiber arrays without the permanent adhesive bonds that complicate repair and rework in deployed data center hardware.
Luxtera (now part of Cisco) pioneered a complementary approach via silicon photonic interposers, where a silicon photonic interposer receives continuous-wave (CW) optical signals from external fibers via grating couplers, processes them based on electrical signals from attached CMOS dies, and transmits electrical output signals via copper pillars to those dies. This architecture separates the optical coupling function from the computation function, enabling independent optimisation of each.
Eindhoven University of Technology’s multi-port optical probe work demonstrates passive optical alignment using flexible waveguide elements in an interposer unit. The PIC chip includes dedicated alignment features for lateral, vertical, and longitudinal passive self-alignment of the flexible waveguide tips to on-chip waveguides — a technique directly relevant to high-volume automated assembly of PIC packages where active alignment is too slow or costly. Research institutions including IEEE have documented the alignment tolerance requirements for photonic packaging as among the tightest in the semiconductor industry.
Fiber attachment is the highest-cost and lowest-yield step in photonic integrated circuit packaging, motivating diverse mechanical approaches including V-groove slots with carrier-layer etch stops, expanded-beam detachable connectors (Intel), and multi-depth multi-stage fiber slots for high-density arrays (GlobalFoundries), each addressing different aspects of alignment precision, reworkability, and manufacturing throughput.
Co-packaged optics and the data center bandwidth wall
The fundamental motivation for PIC packaging in data centers is the impending collapse of electrical I/O scaling. Future-generation processors require optical interconnects to achieve the required compute density and I/O bandwidth because conventional electrical solutions suffer from high signal loss at increasing data rates — and as ASIC processing speeds increase, an I/O system with insufficient optical bandwidth becomes the performance bottleneck preventing the ASIC from operating at its full capability.
Intel’s EMIB/FORDL architecture for CPUs and PICs was explicitly motivated by the need for processors to achieve terabits-per-second I/O bandwidth over distances exceeding 100 metres, as articulated in its 2022 Japanese counterpart patent on integrated photonics and processor package with redistribution layer and EMIB connector. This distance requirement rules out copper-based electrical interconnects entirely at the required bandwidth.
“As ASIC processing speeds increase, the I/O system with insufficient optical bandwidth becomes the performance bottleneck preventing the ASIC from operating at its full capability.”
Google addresses this at the system level via its ASIC packaging approach, where one or more photonic modules — each incorporating a PIC and a fiber array — are attached to the package substrate, with SerDes interfaces connecting the ASIC die to each photonic module. Google’s 2018 Chinese patent on integration of silicon photonic ICs for high data rates identified wire bonding as introducing parasitic inductance that limits scalability for high data rates, proposing vertical flip-chip integration and horizontal tiling on chip carriers as solutions — both described as enabling cost-effective large-volume manufacturing.
Celestial AI’s portfolio is specifically oriented toward PIC packaging for AI accelerator and high-bandwidth memory (HBM) systems. Its core WO 2025 patent family describes the transparent-cavity molded package that enables optical signals to traverse through the encapsulant, bridging the PIC’s passive waveguide layer to external optical interconnects — enabling high-bandwidth photonic data transmission between HBM stacks and AI processor dies within a single package. According to WIPO, photonic packaging has become one of the fastest-growing filing categories in semiconductor packaging patents since 2022.
Nubis Communications targets wafer-scale AI processors in its 2024 US patent on high-capacity optical input/output for data processors, deploying arrays of PICs near the edges of wafer-scale processing modules. Each optical I/O module converts optical signals from external links to electrical signals for the processor array, and converts outbound electrical signals back to optical for transmission. Signal propagation loss on the wafer-level connections is explicitly managed through path length minimisation.
Track co-packaged optics patent activity across Intel, Celestial AI, TSMC, and 10+ other assignees in real time.
Explore Patent Data in PatSnap Eureka →Huawei/Futurewei’s 2015 WO patent on scalable photonic packet architectures using PIC switches deploys silicon photonic PIC switches within data center fabric architectures, using compact silicon photonic circuits arranged in both centralised and distributed configurations, with NxN SiP optical switch matrices at each rack group and 1xP SiP switches providing paths to core photonic switches. This all-photonic switching fabric eliminates electrical-to-optical conversion at intermediate switching nodes, directly reducing latency and power per bit in the data center spine-leaf topology.
TSMC’s co-packaged switching approach integrates a photonic die, an electronic die, and a switch ASIC within a single interconnect package. Components from the electronic die — including SerDes circuits, transceivers, clocking circuits, and control logic — are integrated directly into the switch ASIC to reduce inter-package signal paths. The photonic die is then attached and electrically connected directly to the integrated switch ASIC, eliminating the pluggable optics module entirely. The Semiconductor Industry Association has highlighted co-packaged optics as one of the key technology transitions required for next-generation data center infrastructure.
Lightmatter’s 2022 WO patent on electronic-photonic processors applies PIC packaging to photonic matrix multiplication for AI inference acceleration: multiple PICs, each implementing a photonic accelerator performing matrix operations in the optical domain, are coupled to one side of an interposer while an ASIC controller is attached to the opposite side. Thermal management is handled by dedicated heat spreaders for the PICs and a separate lid for the ASIC, recognising that PIC and EIC thermal profiles differ substantially.
Co-packaged optics (CPO) integrates photonic transceivers directly adjacent to ASICs, GPUs, or switch silicon within the same semiconductor package, eliminating the I/O bandwidth bottleneck caused by separate pluggable optics modules and enabling terabits-per-second I/O bandwidth over distances exceeding 100 metres.
Key assignees and the global patent landscape
Analysis of the patent dataset — comprising more than 60 sources spanning filings across US, WO, EP, KR, CN, JP, NL, DE, SG, TW, and CA jurisdictions, with publication dates ranging from 2006 to 2026 — reveals clear stratification among assignees by both patent volume and architectural scope. The concentration of recent filings from 2022 to 2026 reflects a sharp acceleration in PIC packaging innovation driven by exponential data center bandwidth demands.
Intel Corporation is the single most prolific assignee, with filings across US, WO, EP, KR, CN, NL, and JP jurisdictions covering cavity-based PIC embedding, interposer-mounted PICs, EMIB/FORDL co-packaging, stacked PIC dies, V-groove fiber attachment, expanded-beam detachable connectors, and glass-substrate multi-die packages. Intel’s breadth suggests a platform approach — developing multiple interchangeable packaging architectures rather than a single proprietary solution.
Celestial AI Inc. holds a tightly focused portfolio around transparent-cavity molded PIC packaging and precision copper-pillar EIC-on-PIC stacking, with filings in US, WO, KR, and CN. Its IP directly addresses the HBM and AI accelerator market. Samsung Electronics and Samsung Electro-Mechanics contribute substrate-embedded PIC technology and full optical engine unit packaging, targeting memory-integrated photonic packages directly positioned for next-generation HBM modules with integrated photonic I/O.
Raipac Co., Ltd. (Korea) has built a coherent O-SIP product family covering optical modules, transceivers, and system-in-package configurations across multiple Korean patent filings, with focus on laser diode integration into the molded package alongside PIC and EIC. Advanced Micro Devices (AMD) contributes the dual-mold fan-out RDL module architecture, directly relevant to integrating PICs with AMD’s CPU and GPU chiplet ecosystem. Lightmatter Inc. occupies a distinct niche as a photonic AI compute company, with its photonic interposer and matrix-multiplication PIC packages documented across WO and KR filings.
Google and Huawei/Futurewei represent the hyperscaler and networking equipment perspectives respectively, each deploying PIC packaging at the system integration level for data center switching and AI ASIC packaging. An important geographic trend: the dataset shows significant Korean and Chinese patent activity alongside US and European filings, indicating that PIC packaging has become a globally contested technology domain — not merely a Western semiconductor story. Patent offices including the EPO have reported accelerating filings in photonic packaging technology since 2022.
The PIC packaging patent dataset spans more than 60 sources across US, WO, EP, KR, CN, JP, NL, DE, SG, TW, and CA jurisdictions from 2006 to 2026, with Intel Corporation as the dominant assignee by filing volume, followed by Celestial AI Inc., Samsung Electronics/Samsung Electro-Mechanics, and Korean specialist Raipac Co., Ltd.
The stacking of multiple PIC dies with optical bridges addresses the yield and cost scaling challenge: as PIC die sizes grow to support more channels, yield per die drops. Intel’s stacked PIC die technology allows smaller, higher-yield PIC tiles to be optically coupled and assembled into a larger effective PIC, reducing cost and enabling multi-technology integration within the same package. This approach — tiling smaller dies rather than growing a single large die — mirrors the chiplet strategy that has proven effective in electronic IC scaling and is now being applied to the photonic domain.