The Memory Wall Problem PIM Is Built to Solve

Data movement between off-chip memory and compute units consumes more than 60% of total system energy in modern data-intensive architectures — a bottleneck that conventional von Neumann design cannot resolve by adding more processor cores or faster interconnects. Processing-in-Memory (PIM) architecture addresses this structural inefficiency by co-locating computation capabilities within or immediately adjacent to memory arrays, eliminating the energy and latency cost of shuttling data across the memory bus.

The field encompasses two principal sub-paradigms. Processing-Near-Memory (PNM) places logic layers adjacent to memory — for example, in 3D-stacked DRAM logic layers — preserving standard memory interfaces while enabling higher bandwidth access. Processing-Using-Memory (PuM) performs computation using the intrinsic analog or digital properties of memory cells themselves: charge sharing in DRAM rows, resistive switching in crossbar arrays, or magnetic states in MRAM cells. A third emerging strand, Computational Storage / In-Storage Computing (ISC), extends the paradigm into flash and NVMe storage devices, as reviewed in a 2023 survey from Ain Shams University.

Memory technologies enabling PIM span DRAM, SRAM, Resistive RAM (ReRAM/RRAM), Phase Change Memory (PCM), Magnetoresistive RAM (MRAM/STT-RAM), ferroelectric RAM, and skyrmion-based racetrack memories. Each technology imposes distinct trade-offs in density, endurance, latency, and analog compute fidelity — a diversity that has produced four distinct technology clusters in the innovation landscape, as analysed across 70+ patent and literature records spanning 2014 to 2023.

Four Technology Clusters Defining the PIM Landscape

The PIM innovation landscape is organized around four distinct technology clusters, each targeting different memory substrates, compute models, and deployment contexts. Understanding these clusters is essential for mapping IP white spaces and identifying where commercialization pressure is building fastest.

Cluster 1: DRAM-Based Processing-Using-Memory (PuM)

DRAM-based PuM exploits charge-sharing and bitline sensing physics in standard DRAM arrays to perform bulk bitwise operations without adding logic transistors to the memory die. Its key strategic advantage is commodity DRAM compatibility — enabling deployment without hardware replacement. ETH Zurich’s SIMDRAM framework (2021) proposes a three-step process enabling general-purpose complex operations in commodity DRAM. The University of Coimbra’s pLUTo work (2022) extends this to lookup-table operations supporting multiplication, division, and exponentiation — operations well beyond simple Boolean logic. ETH Zurich’s PiDRAM (2022) delivered the first flexible end-to-end system integration framework for real commodity DRAM-based PuM, addressing host-system integration challenges including virtual address translation and coherence.

Cluster 2: Resistive / Non-Volatile Memory In-Memory Computing

Crossbar arrays of resistive switching devices perform analog vector-matrix multiplication (VMM) in situ, exploiting Ohm’s Law and Kirchhoff’s Current Law to compute neural network dot products with massive parallelism. This cluster dominates AI accelerator proposals in the dataset. According to IEEE-published research from Tsinghua University’s Beijing Innovation Center for Future Chips (2022), RRAM-CIM macro-level circuit designs offer material energy and area advantages over von Neumann architectures for data-intensive AI tasks. CEA-List and Université Grenoble Alpes delivered hardware-verified RRAM IMC with resilience demonstrated through one million endurance cycles — including the first MLC 2-bit adder in RRAM IMC — with up to 16 parallel operations validated in silicon.

Cluster 3: SRAM-Based Compute-in-Memory (CIM)

Modified SRAM bitcells — typically 8T, 9T, or 12T configurations — add read ports or computation paths that perform Boolean logic or analog multiply-accumulate operations directly within the SRAM array. This approach is CMOS-compatible and targets inference-optimized edge and SoC deployments. Sun Yat-sen University’s DM-IMCA (2020) achieved up to 257× performance improvement and 3× SRAM energy savings versus baseline using a 9T bitcell-based CIM with dual operating modes and a custom ISA. Illinois Institute of Technology’s 8T SRAM design (2021) decouples read/write paths for high energy efficiency in binary neural network inference.

Cluster 4: Logic-in-Memory with Emerging Devices and Chiplet / 3D Integration

This cluster combines novel magnetic technologies — MRAM, skyrmion racetrack memory — with advanced packaging strategies (chiplet, 3D-stacked, monolithic 3D) to deliver non-volatile, high-density PIM. Politecnico di Torino’s skyrmion Logic-in-Memory architecture (2021) targets maximum/minimum search operations validated via physical simulation. Halmstad University’s MagCiM processor (2022) uses Magnetic Tunnel Junction (MTJ) mCell memory with near-zero leakage power and CMOS-compatible fabrication. Shanghai Sharetek Technology (2022) reviewed 2.5D, 3D, and fan-out chiplet packaging strategies that physically integrate processor cores and memory dies to break the storage wall.

Application Domains: Where PIM Delivers the Largest Gains

PIM architecture delivers the greatest performance and energy benefits in workloads that are memory-bandwidth-bound, exhibit low data reuse, or involve irregular access patterns — characteristics that make conventional cache hierarchies ineffective. Five application domains dominate the retrieved literature and patent records.

AI and Neural Network Inference

The largest application cluster in this dataset centers on AI inference, where the vector-matrix multiplication (VMM) kernel central to deep neural networks maps directly onto ReRAM and SRAM CIM crossbar array architectures. This includes binary neural networks (Illinois Institute of Technology, 2021), convolutional neural networks (Fraunhofer IPMS, 2021), and deep learning recommendation models. Meta Platforms’ DLRM workload leverages Storage Class Memory in software-defined memory hierarchies to handle terabyte-scale embedding tables — a scale that overwhelms conventional DRAM bandwidth.

Genomics and Bioinformatics

DNA sequence alignment is a memory-bandwidth-bound workload with irregular access patterns that makes it an ideal PIM target. Technion Israel Institute of Technology’s Resistive CAM (ReCAM) architecture demonstrated 4.7× throughput improvement and 15× lower power versus GPU-based Smith-Waterman alignment — a result that has made Technion a consistent contributor to PIM bioinformatics research. Carnegie Mellon University’s FPGA-based near-memory acceleration work (2021) demonstrated pre-alignment genome filtering speedups over IBM POWER9 using FPGA-coupled HBM.

Graph Processing and Databases

Graph analytics and database operations exhibit low data reuse and irregular memory access — exactly the workloads for which PIM delivers the largest gains, as established by ETH Zurich‘s landmark benchmarking studies (2021–2022). These studies provided empirical, hardware-verified performance characterization of real PIM systems on neural network inference, graph processing, and database workloads — moving PIM evaluation from simulation to measured silicon results.

IoT and Edge Computing

Low-power PIM for sensor data processing is emerging as an application domain, with LUT-based PIM in Phase Change Memory targeting energy-constrained IoT front-end nodes. ShanghaiTech University’s 2023 streaming data processing architecture extends a RISC-V ISA with PCM-based LUT lookup, replacing online arithmetic for IoT sensor streams — a design that directly addresses the energy budget constraints of edge deployments.

High-Performance Computing and In-Storage Computing

Sparse pattern processing — document search, NLP, subgraph matching — benefits from in-storage accelerators. MIT’s 2016 flash-embedded accelerator handled up to 1TB of data while matching 48-core server performance at a fraction of the power, an early demonstration of the in-storage computing paradigm that standards bodies including JEDEC are now beginning to address through interface standardization efforts.

“Data movement between off-chip memory and compute units constitutes a dominant cost in both energy and latency — frequently exceeding 60% of total energy in modern systems.”

Geographic and Institutional Innovation Leaders

Innovation in PIM architecture is broadly distributed across academic institutions and national laboratories rather than concentrated in a few corporate assignees — a pattern that reflects both the fundamental research maturity of the field and the significant remaining engineering gaps before full commercialization. The following geographic and institutional patterns are observable within this dataset.

Switzerland (ETH Zurich) accounts for at least 6 distinct retrieved publications (2020–2022), covering SIMDRAM, CLR-DRAM, PiDRAM, benchmarking studies, and data-centric architecture frameworks. South Korea has strong representation across Seoul National University, Korea University, and Yonsei University, with Korea University’s 2022 all-bank PIM paper addressing JEDEC standardization pathways — a critical commercialization signal. China contributes through multiple institutions: Tsinghua University’s Beijing Innovation Center for Future Chips (RRAM-CIM), Fudan University (non-volatile TCAM for AI), Sun Yat-sen University (SRAM-CIM), ShanghaiTech University (LUT-based streaming PIM, 2023), and Xidian University (chiplet-based systems).

United States institutions present a diverse base — Carnegie Mellon University, MIT, Purdue University, Georgia Institute of Technology, Colorado State University, and Oak Ridge National Laboratory (2023 comprehensive survey). Israel‘s Technion Institute of Technology is a consistent contributor to memristive stateful logic, compilation flows, and DNA sequence alignment applications. Italy‘s Politecnico di Torino and Politecnico di Milano are active in logic-in-memory paradigms and emerging device architectures. France‘s CEA-List and Université Grenoble Alpes delivered hardware-verified RRAM IMC demonstrations, while IMEC Belgium produced design automation frameworks.

Corporate assignees in this dataset are limited: IBM holds a GB patent (active) covering FPGA-integrated memory hierarchy (2016); Intel holds an EP patent (active) covering dynamic microarchitectural tuning (2023). Samsung Electronics appears in memory technology literature (2011). The dataset is heavily weighted toward academic publications, suggesting that commercial IP consolidation in PIM is still in early stages — consistent with observations from WIPO on the typical lag between academic publication clusters and commercial patent filing surges in semiconductor architecture fields.

Emerging Directions Shaping PIM Through 2026

The most recent filings and publications from 2022 to 2023 in this dataset reveal five frontier directions that will define the PIM competitive landscape through 2026 — spanning instruction set architecture, packaging, compiler tooling, novel memory devices, and thermal engineering.

1. RISC-V as the Standard PIM Instruction Framework

Two independent 2022 works — University of Twente’s RISC-Vlim framework and ShanghaiTech University’s streaming LUT architecture — both extend RISC-V with custom in-memory computing instructions. RISC-V’s open ISA makes it the default substrate for PIM ISA extension research. No dominant standard ISA extension for PIM has emerged in this dataset, meaning the organization that defines and patents RISC-V PIM instruction extensions and builds associated compiler toolchains will create ecosystem lock-in analogous to SIMD ISA extensions in conventional processors.

2. Chiplet-Based PIM Integration

Advanced packaging — 2.5D interposer, 3D stacking, fan-out — is being positioned as a near-term commercial pathway for PIM, avoiding the need for novel memory process integration. Shanghai Sharetek Technology (2022) and Xidian University (2022) both review chiplet strategies that physically integrate processor cores and memory dies. This approach allows PIM capability to be assembled from existing memory and logic process nodes, reducing the time-to-market risk associated with developing new memory technologies from scratch.

3. Compiler and Programming Model Abstraction

The field is addressing the absence of portable PIM programming by developing technology-agnostic compilation flows. Technion’s abstractPIM (2021) provides a technology backward-compatible compilation flow for PIM — a critical missing layer that currently forces application developers to target specific memory hardware directly. Without portable programming models, PIM adoption is constrained to specialist teams, limiting the addressable market.

4. Non-Volatile TCAM for AI and Parallel Search

Fudan University’s 2022 review documents the convergence of non-volatile memory (ReRAM, PCM, MRAM, ferroelectric) into ternary content-addressable memory (TCAM) architectures that simultaneously serve network packet classification and neural network weight matching. This dual-use capability — search acceleration and AI inference on the same hardware — represents a significant IP opportunity at the intersection of networking and AI acceleration.

5. Thermal and System-Level Co-Design for 3D PIM Systems

As PIM moves to 3D stacking, thermal management becomes a first-order design constraint. IIT Delhi’s CoMeT toolchain (2022) addresses thermal simulation for 2D, 2.5D, and 3D processor-memory systems — an infrastructure capability that will be essential for any organization designing stacked PIM products. The absence of mature thermal co-design tools has been identified by multiple surveys as a blocking issue for 3D PIM commercialization.

Strategic IP Implications for R&D and Patent Teams

The PIM landscape as characterized across 70+ records reveals several high-value IP opportunity areas for organizations seeking to establish defensible positions before commercial consolidation accelerates. Each implication below is grounded directly in the technology and geographic patterns identified in this dataset.

DRAM-based PuM offers the fastest path to deployment. Commodity DRAM compatibility, as demonstrated by the SIMDRAM and pLUTo frameworks, enables PIM capability on existing infrastructure without memory technology replacement. This is a compelling near-term IP opportunity for DRAM vendors and system integrators targeting AI inference and database acceleration — particularly given that Korea University’s JEDEC interface compatibility work (2022) provides a standardization pathway that could make in-DRAM PIM operations transparent to host systems.

ReRAM crossbar arrays are the dominant neural network accelerator bet, but variability and endurance remain blocking issues. CEA-List’s 2022 hardware demonstration — 16 parallel operations, one million endurance cycles, first MLC 2-bit adder in RRAM IMC — represents a milestone. IP positions around variability-tolerant circuit designs and MLC programming for IMC are strategically valuable, as they address the primary engineering barrier to ReRAM-based AI accelerator commercialization, a field that organizations including OECD have identified as a priority area for semiconductor competitiveness policy.

Chiplet packaging is the integration bridge for PIM in HPC and AI accelerators. IP around 2.5D/3D PIM packaging, die-to-die interfaces, and thermal management for stacked compute-memory systems represents a growing opportunity for packaging technology specialists and fabless design houses. The CoMeT thermal simulation toolchain from IIT Delhi (2022) signals that thermal co-design IP is as strategically important as the memory device IP itself for 3D stacked systems.

The RISC-V PIM ISA extension space is open. No dominant standard ISA extension for PIM has emerged in this dataset. Organizations that define and patent RISC-V PIM instruction extensions, and build associated compiler toolchains, will create ecosystem lock-in analogous to SIMD ISA extensions in conventional processors. The abstractPIM compilation flow from Technion (2021) demonstrates that technology-agnostic compiler IP is achievable — and currently uncontested.

System-level resource management and programming models are the critical gap. Multiple surveys identify address translation, coherence, workload partitioning, and thermal management as unresolved system-integration problems. This indicates that middleware, OS, and compiler-level IP is underexplored and strategically valuable relative to device-level IP — a structural opportunity for software-hardware co-design teams. Organizations with IP portfolios at the intersection of IP management and semiconductor architecture will be well-positioned to identify and claim this white space using platforms such as PatSnap’s innovation intelligence tools.