What drives GIDL in thin-body SOI and why it matters for IoT

Gate-induced drain leakage is generated by high electric fields at the gate-to-drain overlap region, which induce band-to-band tunneling (BTBT) of carriers across the reverse-biased drain junction. In thin-body silicon-on-insulator transistors, this effect is amplified because the thin silicon body provides less electrostatic screening and the buried oxide (BOX) removes the bulk charge that would otherwise partially suppress the lateral field. For IoT microcontrollers operating on coin-cell batteries — where standby power budgets are measured in nanowatts — GIDL is not a second-order nuisance but a primary design constraint.

Research from Jordan University of Science and Technology (2020), modeling GIDL alongside drain-induced barrier lowering (DIBL) through band-to-band tunneling expressions validated against BSIM4 references, confirms that aggressive oxide thickness scaling below 5 nm substantially amplifies all leakage channels. This finding is foundational: as IoT microcontroller designers push toward ever-thinner gate dielectrics for performance, they simultaneously worsen the leakage problem they are trying to solve. Understanding the precise physical origin of GIDL is therefore the prerequisite for choosing the right suppression strategy.

In thin-body fin architectures specifically, work from the National Taipei University of Technology (2020) on poly-Si fin-like thin-film transistors (FinTFTs) identifies longitudinal BTBT (L-BTBT) at the intrinsic drift/N+ drain junction as the dominant GIDL mechanism. At elevated temperatures and larger drain extension lengths, generation-recombination and trap-assisted tunneling become co-dominant mechanisms. This transition is critical knowledge for engineers who must validate device behaviour across industrial temperature ranges — a common requirement for IoT sensor nodes deployed in harsh environments.

A comparative study from Universiti Kebangsaan Malaysia (2013) on SOI MOSFET technologies for low-power applications confirms that fully depleted SOI (FDSOI) outperforms both partially depleted SOI (PDSOI) and bulk silicon on all leakage current metrics, including GIDL. The mechanism is the thinner active silicon layer combined with complete electrostatic control afforded by the gate. This positions FDSOI — as standardised and characterised by bodies such as IEEE and widely reported in the literature — as the technology of choice for ultra-low-power IoT microcontrollers where passive leakage during dominant sleep periods must be minimised without sacrificing active-mode drive current.

Structural drain and gate engineering to suppress GIDL at the device level

The most direct way to reduce GIDL is to attack its root cause: the high longitudinal electric field at the gate-to-drain overlap. Two structural approaches have been experimentally validated — wide-drain geometries and stacked gate dielectrics — and both deliver measurable leakage reduction without requiring exotic process modules.

Wide drain and extended drain architectures

Extending or widening the drain in FinTFT and thin-body structures dilutes the longitudinal electric field at the channel-drain junction, directly suppressing the L-BTBT that drives GIDL. Research from the National Taipei University of Technology (2018) shows that in FinTFT structures, the wider drain simultaneously increases the cross-sectional area for current flow, improving ON-state current — a dual benefit that is particularly valuable for IoT applications where both active performance and standby leakage matter.

Follow-on experimental fabrication work from the same group (2020) quantifies the effect precisely: increasing the extended drain length (LEX) progressively reduces the longitudinal electric field magnitude at the intrinsic drift/N+ drain junction. For devices with LEX = 0, BTBT dominates with weak temperature dependence. At LEX = 1.6 µm, the leakage becomes strongly temperature-dependent, indicating a crossover to generation-recombination as the limiting mechanism — which is intrinsically lower in magnitude under room-temperature IoT operating conditions. This crossover is a practical design target: once generation-recombination dominates, the device behaviour becomes more predictable and the leakage floor is lower at the temperatures where IoT nodes actually operate.

Gate dielectric stack engineering: the NAOS stacked oxide approach

Gate insulator quality and thickness profoundly influence GIDL because both the oxide electric field and interface trap density directly affect the magnitude of BTBT at the drain. Research from the Japan Science and Technology Agency (2015) demonstrates that a stacked gate oxide — a 1.4 nm NAOS-grown SiO2 interfacial layer plus an 8.6 nm PECVD SiO2 layer, totalling 10 nm — achieves a two-orders-of-magnitude reduction in off-current in ultra-low-power poly-Si TFTs. The NAOS interfacial layer serves two functions: it blocks gate leakage tunneling, and it improves the nucleation quality of the deposited oxide, reducing interface traps that would otherwise serve as BTBT generation centres.

“A stacked gate oxide with a 1.4 nm NAOS-grown SiO2 interfacial layer achieves a two-orders-of-magnitude reduction in off-current — directly addressing one of the root causes of GIDL in thin-body devices where oxide quality degrades with aggressive thickness scaling.”

This finding directly addresses the paradox identified in the mechanisms section: the same oxide-thinning that improves active-mode performance degrades leakage. The NAOS stacked approach allows designers to achieve equivalent electrical oxide thickness (EOT) targets while maintaining the interfacial quality needed to keep GIDL suppressed. Standards bodies such as the semiconductor industry and process qualification frameworks from organisations including NIST increasingly recognise interfacial layer quality as a primary reliability metric for thin-gate devices.

FDSOI underlap geometry and high-k spacers: the low-leakage design path

The underlap gate geometry — where the gate edge is deliberately set back from the metallurgical source/drain junctions — is the most analytically powerful structural technique specifically calibrated to FDSOI. It reduces the lateral electric field in weak inversion by extending the effective channel length through the underlap spacer region, and the benefits compound when combined with enhanced dynamic threshold operation.

Research from the University of São Paulo (2015) on extensionless ultra-thin-body and buried-oxide (UTBB) FDSOI devices demonstrates that underlap devices exhibit lower IOFF, lower subthreshold swing, lower GIDL, higher gm/ID ratio, and higher intrinsic voltage gain compared to standard devices — all simultaneously. The enhanced dynamic threshold (eDT) mode, which ties the back gate voltage to a fraction of the front gate voltage (VB = kVG), further boosts ION while maintaining the same IOFF. For IoT microcontrollers that spend most of their time in sleep but must wake rapidly to process sensor data, this configuration is compelling: it delivers the low-leakage floor needed for sleep and the drive current needed for fast wake-up without separate device types.

A complementary modeling study from Thapar Institute of Engineering and Technology (2021) on underlap strained silicon-on-insulator MOSFETs identifies a practical limitation of the underlap approach: increasing underlap length degrades ON-current because the gate loses control over the lightly doped spacer region. The solution is a high-k dielectric spacer material in the underlap region, which compensates for this degradation by enhancing gate controllability over the underlap channel region. The result is a high ION/IOFF ratio maintained across the design space, confirming this as a viable low-power FDSOI design path for IoT microcontrollers. Technical guidance on high-k dielectric integration is available through organisations such as the semiconductor process community and standardised through bodies including IEEE.

Circuit-level techniques: back-gate bias, power gating, and gate under-driving

Device-level GIDL suppression is necessary but not sufficient for a complete IoT microcontroller design. Circuit-level techniques — particularly those that exploit the unique back-gate access of FDSOI and the negative-voltage capability of modern power management ICs — provide a complementary and often synergistic layer of leakage control.

Dynamic threshold voltage control via FDSOI back gate

Thin-body FDSOI transistors offer a capability unavailable in bulk CMOS: the back gate voltage can modulate the front-channel threshold voltage without forward-biasing any junction. A US patent by Ashenafi (2019) explicitly describes this architecture — the back gate of an FDSOI transistor controls the threshold voltage to eliminate standalone sleep transistors, integrating sleep and logic functions in a single device. During sleep, a high back-gate bias raises VT and suppresses GIDL; during active computation, a low back-gate bias lowers VT and maximises drive current. This eliminates the area and power overhead of dedicated sleep transistors, which is significant in constrained IoT silicon budgets.

The concept extends further to junctionless SOI FETs. Research from the National Institute of Technology Patna (2021) shows that a buried metal fin (BMF) of appropriate work function can modulate the channel electrostatic field through Schottky junction coupling, achieving a body factor (γ) enhancement and broad VT tunability. The dynamic threshold mode of the BMF-SOI-JLFET provides a 73% improvement in ON-state current compared to conventional SOI junctionless FETs while maintaining reduced subthreshold swing — a configuration that inherently suppresses GIDL by raising effective VT in the off-state without any additional process steps.

Negative-voltage sleep transistor circuits

Patents from Mosaid Technologies (2010, 2012) describe an adaptive leakage controller that applies a negative voltage generated by a charge pump to sleep transistors cascaded to logic gates. The negative gate-source voltage (VGS) applied to the off-state transistor increases its effective threshold voltage in real time, directly suppressing both subthreshold and GIDL components of off-state current. This approach is particularly effective in thin-body SOI transistors with floating bodies, since it prevents the accumulation of holes at the drain end that would otherwise enhance BTBT.

Hierarchical power supply and gate under-driving

Mitsubishi Electric’s family of patents (US, 2002, 2004, 2005) establishes the principle of using transistors with large gate tunnel barriers — thick gate oxide — as the standby-on devices, reserving thin-gate-oxide MIS transistors for active computation. By structurally separating high-leakage thin-oxide transistors from the standby power domain through a hierarchical supply architecture, gate tunneling current is reduced during standby. This hierarchical power supply concept maps directly onto modern IoT microcontroller architectures that retain small always-on domain transistors in sleep, a design pattern now widely adopted across the industry and documented in standards from JEDEC.

Xilinx’s 2007 patent on sub-threshold leakage suppression introduces gate under-driving: applying a VGS below 0 V to transistors in their off state significantly reduces sub-threshold leakage without affecting on-state performance. In thin-body SOI transistors with floating bodies, this technique also reduces the drain-to-body electric field component that drives GIDL, as the more negative gate potential lowers the field at the gate-drain overlap region.

Who is innovating: key institutions and patent clusters

The GIDL suppression landscape for thin-body SOI and IoT applications is shaped by a small number of institutional clusters, each contributing distinct technical depth. Understanding who holds the key IP and where the academic frontier sits is essential for engineers navigating freedom-to-operate and technology licensing decisions.

National Taipei University of Technology is the most prolific source of direct GIDL characterisation data, with multiple studies on FinTFT wide-drain structures showing quantified GIDL reduction through both simulation and fabricated device measurement. Their work specifically targets the L-BTBT mechanism in thin-body fin architectures and provides the most granular experimental data on the LEX design variable.

University of São Paulo (LSI/PSI) contributes the most targeted FDSOI GIDL analysis in the dataset, specifically quantifying GIDL suppression in UTBB FDSOI underlap devices and their enhanced dynamic threshold variants. Their work is directly applicable to IoT microcontroller design because it models the full active/sleep duty cycle.

Mosaid Technologies / Conversant Intellectual Property Management holds the broadest patent portfolio in the dataset on adaptive leakage control circuits using negative-voltage sleep transistor networks, with active or historically influential patents in multiple jurisdictions including the US, EP, IL, CN, and TW. These represent key circuit IP for IoT sleep-mode power management and are relevant to any designer implementing power-gating in a product.

Mitsubishi Electric pioneered hierarchical power supply architectures with gate-tunnel-current reduction mechanisms across multiple US patents (2002, 2004, 2005), establishing foundational circuit topology for standby power minimisation in integrated circuits containing thin-gate transistors. Their work predates the IoT era but maps directly onto modern always-on domain architectures.

Shin-Etsu Handotai holds multiple active patents (US and EP, 2017) on SOI substrate evaluation methods linking interface state density to leakage power. This metrology infrastructure is essential for qualifying thin-body SOI wafers for IoT microcontroller fabrication — connecting wafer-level quality control to device-level GIDL performance. Wafer qualification standards are also addressed by international bodies including SEMI.

Japan Science and Technology Agency provides critical process-level insight into gate dielectric engineering (NAOS stacked oxide), demonstrating two-orders-of-magnitude off-current reduction and establishing the importance of gate insulator quality in GIDL suppression. Thapar Institute of Engineering and Technology and National Institute of Technology Patna represent emerging academic contributors producing compact modeling and novel device architectures — underlap SSOI and buried-metal-fin SOI junctionless FETs — with direct relevance to GIDL and ION/IOFF optimisation.