The Physical Root Cause: Parasitic Capacitance and Common-Mode Voltage

Leakage current in transformerless PV inverters originates from parasitic capacitance between PV panels and their grounded metal frames. When the inverter switches, it generates a high-frequency common-mode voltage across this capacitance, driving current through the resulting common-mode loop. Research from Aswan University (2021) confirms that this current can reach hazardous magnitudes when a resonance circuit is excited through the PV parasitic capacitance and the converter’s inductive components.

Research from Universidad Autónoma de Querétaro (2020) further clarifies that the leakage current magnitude depends on both the value of the parasitic capacitances and the common-mode voltage profile generated by the chosen modulation strategy—meaning hardware topology and software control are both decision variables, not independent of one another. Work from Chonnam National University (2022) confirms that this relationship holds in three-phase systems as well, where the common-mode voltage waveform directly determines the leakage current frequency spectrum and amplitude.

Non-compliance carries consequences beyond personal safety. Research from Missouri University of Science and Technology (2020) quantifies the secondary effects of excessive leakage current: increased current harmonics injected into the utility grid, elevated radiated and conducted electromagnetic interference (EMI), and additional conversion losses. These degrade overall system performance independently of the safety concern, creating a strong commercial as well as regulatory incentive for suppression. Standards bodies including IEC and VDE continue to tighten these thresholds as transformerless architectures become the global commercial norm.

Topology-Level Strategies: H-Bridge Variants, Common-Ground, and Multilevel Architectures

Topology selection is the most fundamental design decision for leakage current suppression because it determines whether the common-mode voltage path exists at all. Three families of topology have emerged as the dominant commercial and research responses: modified H-bridge circuits, common-ground architectures, and multilevel inverters.

Modified H-Bridge Variants: H5, H6, H7, HERIC

The most commercially mature approach involves modifying the standard full-bridge (H4) inverter with additional switches or diodes that decouple the AC and DC sides during freewheeling intervals, preventing the common-mode voltage from varying at switching frequency. Research from Jawaharlal Nehru Technological University (2022) provides a systematic analysis of H4, H5, H6, and HERIC topologies alongside unipolar and bipolar PWM strategies, establishing the trade-offs between efficiency, component count, and leakage suppression effectiveness.

The H7 topology adds a seventh switch with a series diode to clamp the common-mode voltage to the DC-link midpoint during zero states. Research from Aalto University (2020) demonstrates that bipolar sinusoidal PWM combined with the H7 structure achieves effective common-mode leakage current mitigation in a single-phase utility grid, extending the approach as an improvement over the H6 topology. A three-phase H7 variant from Taif University (2021) splits the boost converter inductance to further reduce earth leakage current. The patent from Integral University (2023) formalizes the combined decoupling-and-clamping architecture: AC and DC sides are decoupled, and one bridge leg voltage is clamped to the DC-link midpoint via two additional switches and a diode, with both mechanisms activated during the freewheeling state—keeping THD and efficiency largely unaffected.

Common-Ground Topologies

Common-ground topologies represent the most structurally definitive approach to leakage current elimination. By directly connecting the negative terminal of the PV modules to the grid neutral, the leakage current path is severed by design rather than by modulation control. Research from Aswan University (2021) identifies this as the most effective among all known strategies because it offers a solid, permanent connection that does not depend on switching state. The Instituto Tecnológico de Celaya (2018) implements this principle in a current-source inverter architecture, directly connecting the grid neutral line to the PV system’s negative terminal and theoretically eliminating any leakage current through that terminal—while also reducing inductor size compared to conventional current-source inverters.

A system from Malaviya National Institute of Technology Jaipur (2024) achieves zero common-mode voltage by connecting the source negative rail and grid neutral terminals to ground through a configuration using six switches, two diodes, and two self-balancing capacitors rated at half the maximum grid voltage. A companion multilevel topology from the same institution (2020) presents a five-level transformerless design that completely eliminates common-mode leakage current while providing inherent voltage boosting via switched capacitors, without requiring any magnetic boosting components.

Multilevel Inverter Topologies

Multilevel inverters offer a dual benefit for transformerless PV applications: they reduce output current THD through finer voltage step resolution while simultaneously enabling operating modes that maintain constant common-mode voltage. A five-level topology from Imam Khomeini International University (2022) presents two alternative connection models that stabilize common-mode voltage and reduce leakage current, with five output voltage levels reducing harmonic distortion compared to two- and three-level designs. A six-level topology from the University of Tabriz (2022), combining six power switches and two diodes, was validated on a 770 W laboratory prototype and provides full reactive power support along with voltage boosting. A seven-level common-ground topology from S.A. Engineering College, Chennai (2023) extends the concept further with triple voltage boost and self-balanced capacitor voltages without complex control algorithms.

“Multilevel topologies simultaneously address leakage current and THD: five-, six-, and seven-level designs naturally reduce the rate of change of common-mode voltage and lower output harmonic content.”

Modulation and Control-Level Suppression

Modulation strategy selection is the lowest-cost intervention point for leakage current reduction because it requires no hardware changes. The core principle is that modulation schemes which maintain a constant common-mode voltage—or which produce only low-frequency common-mode components—inherently minimise leakage current through the parasitic capacitance.

Research from the University of Sheffield (2018) demonstrates that conventional phase-shifted PWM fails to suppress leakage current in cascaded H-bridge inverters. The authors propose a switching-state-aware modulation scheme that ensures compliance with VDE-0126-1-1 by selecting only those switching states that prevent high-frequency common-mode voltage components—directly addressing a topology that is otherwise structurally favourable for PV applications due to isolated DC sources. According to IEEE publications on power electronics, switching-state selection in multilevel modulation is an active area of standardisation and research.

Ginlong Technologies Co., Ltd. (2025) takes a system-level modulation approach: synchronous carriers are applied to multiple parallel inverters in a string, and switching states are controlled so that common-mode components from individual inverters are dislocated and partially cancel each other. This is described as a pure software optimisation requiring no additional hardware, making it particularly attractive for retrofit or firmware-update deployment across installed string inverter fleets.

SMA Solar Technology AG’s active patent formalises the operational control loop concept: leakage current is measured in real time and fed back into the inverter’s operational control to ensure that predetermined maximum values are not exceeded during all operating conditions. This closed-loop approach is topology-agnostic and can be applied alongside any of the hardware strategies described above. Huawei Digital Power Technologies (2022) implements a sampling control unit that detects the leakage current formed by common-mode voltage on the parasitic capacitor and adjusts the injection amount of common-mode voltage in the PWM pulse sequence accordingly—a tightly integrated sense-and-suppress loop.

For quasi-Z-source inverters (qZSI), research from Aalborg University (2020) shows that conventional common-mode voltage reduction strategies developed for voltage-source inverters cannot be directly applied to qZSI due to the extra shoot-through state. An input-split-inductor qZSI topology is introduced to decouple the common-mode voltage from the shoot-through state, enabling standard reduction strategies to be applied without modification. A dual common-mode inner loop approach from Hangzhou Dianzi University (2018) addresses the limitation of single common-mode inner loop control—which performs poorly at low PV output power and fails to suppress high-frequency resonance—by substantially reducing high-frequency components across the full power range.

Passive and Active Filter Approaches

When topology modification and modulation optimisation alone are insufficient—particularly in retrofit scenarios or under variable environmental conditions—passive and active filter elements provide an additional suppression layer that can be applied independently of the inverter control architecture.

The Florida State University Research Foundation holds patents on passive filter solutions for cascaded multilevel inverters (2016 and 2017). Both present properly arranged passive filters that suppress leakage current in cascaded multilevel inverters without requiring additional active semiconductor devices, preserving the structural simplicity of the cascaded topology and avoiding complications to the associated control system. Research from the Instituto Tecnológico Superior de Irapuato (2022) introduces a DC-link-tied LC output filter configuration for a five-level cascaded H-bridge inverter. The mathematical model demonstrates that this specific passive filter connection provides leakage ground current reduction regardless of the PWM strategy applied—making it a PWM-agnostic hardware solution.

Research from Tecnológico Nacional de Mexico/ITS de Irapuato (2023) adds a passive inductive-capacitive output filter to the high-efficiency inverter structure specifically to reduce the dependency of leakage ground current on system power and weather conditions. The inductive-capacitive filter provides a low-impedance path for leakage current that is different from the ground path, effectively redirecting it. Research from Taizhou University (2021) proposes paralleling an output filter capacitor with the parasitic capacitances to suppress ground current in full-bridge inverters using unipolar or hybrid PWM, reducing the effective impedance at the leakage current node without adding active components. Standards bodies such as IEC and energy regulators tracked by IEA increasingly require documented filter performance as part of grid-connection approval processes.

For active suppression, a patent from Taizhou University (2014) proposes a circuit composed of common-mode voltage detection, grid voltage detection, voltage followers, and a common-mode transformer. The device injects a compensation signal into the output side of the non-isolated inverter to cancel the total common-mode voltage—and additionally addresses leakage current caused by imbalanced output filter inductors by connecting the DC bus capacitor midpoint to the grid ground. Research from the University of Mazandaran (2022) extends the problem scope to environmental mismatch conditions—partial shading and temperature variation—that cause voltage imbalance in PV arrays and increase common-mode current. A compensation circuit is proposed to offset the voltage drop from these conditions, addressing a failure mode not covered by standard topology or modulation solutions.

Leakage Current Monitoring and Compliance Verification

Effective suppression requires accurate real-time measurement: without reliable sensing, neither closed-loop control nor threshold-based protection can operate correctly. LSIS Co., Ltd. holds a family of active patents in both the US and EP jurisdictions covering a specialised monitoring apparatus with a consistent architecture across all filings.

The LSIS monitoring architecture operates as follows: a low-pass filter removes high-frequency noise from the sensed leakage current signal; an average value calculator isolates the DC component; a DC component remover subtracts it; a phase-locked loop circuit extracts the peak value and phase; and a resistive component leakage current calculator determines the resistive component of the leakage current. This resistive component is specifically the safety-relevant portion monitored against IEC 62109 thresholds. LSIS also holds an active US patent on a single-phase PV inverter that uses a small insulated transformer and an ordinary current transformer to measure leakage current, replacing the high-priced dedicated current transformer otherwise required—lowering the barrier to compliance monitoring in residential-scale systems.

Huawei Digital Power Technologies addresses the sensing-to-control loop integration in its US (2023) and EP patents, where the sampling control unit detects the leakage current formed by common-mode voltage on the parasitic capacitor and adjusts the common-mode voltage injection amount dynamically in the PWM sequence. The Jiangsu Electric Power Research Institute (2023) proposes a four-subsystem architecture: current acquisition, data processing, leakage current discrimination, and suppression actuation. The system samples true leakage current via a current transformer, calculates the RMS value over one cycle at every sample point, compares against threshold, and actuates suppression measures when the threshold is exceeded—a practical implementation framework for compliance monitoring in deployed single-phase inverters. Research bodies including NREL have highlighted integrated sensing as a critical gap in field-deployed PV inverter compliance infrastructure.

Key Players and the Direction of Innovation

The patent and literature dataset reveals a clear competitive structure: industrial assignees dominate closed-loop control and monitoring IP, while academic institutions drive topology innovation—particularly in multilevel and common-ground architectures.

LSIS Co., Ltd. is the most prolific patent holder in monitoring apparatus, with at least four active patents (two US, two EP) covering essentially the same resistive-component leakage current measurement architecture, reflecting a clear IP protection strategy for their commercial monitoring product line.

Huawei Digital Power Technologies Co., Ltd. holds multiple active patents (US and EP) focused on closed-loop common-mode voltage control integrated with the inverter control system, representing a vertically integrated approach from sensing through suppression in commercial-scale string and central inverters.

SMA Solar Technology AG holds active patents on the operational control method for leakage current, emphasising the regulatory compliance angle of keeping leakage current below predetermined maximums through active control—consistent with SMA’s long-standing leadership in residential and commercial transformerless inverter products in European markets.

The Florida State University Research Foundation focuses on passive filter solutions for cascaded multilevel inverters, with one active and one inactive US patent, signalling academic-to-commercial technology transfer interest in the multilevel topology segment.

Ginlong Technologies Co., Ltd. has two recently active US patents (both 2025 grant/publication dates) on the carrier-dislocation method for string inverter systems, representing a purely software approach to leakage suppression in parallel-inverter string configurations—likely targeting the large-scale utility segment.

Malaviya National Institute of Technology Jaipur appears in multiple literature entries and patents covering common-ground boosting inverters and multilevel topologies, establishing it as a significant academic contributor to the topology innovation segment in India. The PatSnap IP Analytics platform provides assignee-level patent portfolio benchmarking across all these players, enabling R&D teams to identify white-space opportunities and freedom-to-operate risks before committing to a topology or control strategy. Teams can also use PatSnap R&D Intelligence to map the full citation network across this literature corpus.

In terms of innovation trajectory, the dataset shows a clear evolution: early work (2015–2018) focused on H5/H6/HERIC modifications; the 2019–2021 period saw rising interest in current-source inverters, multilevel topologies, and quasi-Z-source architectures; from 2022 onward, the focus has shifted toward six- and seven-level topologies, mismatch-condition robustness, system-level string approaches, and integrated sensing-and-control architectures. This trajectory aligns with the broader solar industry trend tracked by IRENA toward higher-power, utility-scale string inverter deployments where software-defined compliance verification is commercially preferable to hardware redesign.