The Gate Capacitance Energy Problem at High Frequencies

In conventional gate driver circuits, every switching event dissipates the energy stored in the gate capacitance of the power switch as heat in gate resistors. This loss scales directly with switching frequency — and at hundreds of kilohertz to megahertz, it becomes the dominant loss mechanism in the driver stage. General Electric Company’s 2002 patent on high-frequency resonant gate drivers for MOS-gated power switches quantified this precisely: for a 1200 V/600 A IGBT switching at 62 kHz, conventional gate drive power loss reaches 9 W, all dissipated in gate resistors. At the multi-megahertz frequencies enabled by GaN HEMTs, the same scaling law makes resistive gate driving untenable for data center PSU efficiency targets.

The fundamental mechanism of resonant gate driving replaces the resistive discharge path with an inductive resonant path. Gate capacitance charge and discharge then occurs sinusoidally rather than exponentially, allowing the stored charge to be partially returned to the supply rather than converted to heat. This was formalised in a dual-path architecture described in the 2013 US patent by Marco Cioci: a resonant path couples the gate of a power transistor to a supply capacitor during charging and discharging, while a separate low-impedance path couples the gate to a voltage rail when neither operation is occurring. According to IEEE power electronics literature, this selective use of resonant versus low-impedance paths is the central design principle enabling gate charge to be partially returned to the supply rather than dissipated.

Queen’s University at Kingston extended this concept to high-current gate drive using a full-bridge inductor-based implementation. A circuit comprising four bidirectional semiconductor switches in a full-bridge configuration with an inductor across the bridge junction uses the inductor as a current source to charge and discharge the gate capacitance with high current. This approach simultaneously reduces switching transition time — which reduces overlap loss in the main power switch — and recovers gate energy. The gate voltage can be clamped to on-state or off-state levels between switching transitions, preserving compatibility with PWM control schemes used in data center PSUs. Queen’s University holds at least six patents across US, CA, and WO jurisdictions covering this family of circuits, including variants with centre-tapped transformers and current source drivers capable of generating negative gate voltage — a feature critical for GaN HEMTs with low threshold voltages where a sufficiently negative off-state voltage prevents false turn-on under high dv/dt conditions.

Koninklijke Philips Electronics added a further refinement: discrete capacitors within the resonant circuit maintain resonance at a target frequency independently of parasitic capacitance variation. This is a critical engineering consideration when GaN devices are substituted into an existing design, because GaN HEMTs’ gate capacitance differs from silicon MOSFETs and can shift the resonant frequency outside the driver’s operating window. General Electric’s 1991 lossless gate driver patent documented the earliest architecturally complete embodiment: a series resonant circuit making resonant energy transfers between gate input capacitance and a storage capacitor, with timing circuitry ensuring proper sequencing relative to AC switch operation.

Charge recycling between high-side and low-side gates provides an additional energy recovery mechanism in half-bridge configurations. A 2013 patent by Shangzhi Pan describes a coupling inductor that circulates energy between high- and low-side gates while simultaneously acting as a voltage-boost transformer. A comparable charge-recycling architecture — validated in silicon at the IC level by Sungkyunkwan University in 2019 — demonstrated up to 87.7% reduction in gate-driving loss using charge recycling with variable gate-voltage swing in a 65 nm CMOS test chip, with 90.3% peak power conversion efficiency.

Soft-Switching Topologies and Gate Driver Interaction in GaN Converters

The efficiency benefits of resonant gate driving are most fully realised when the main power converter topology also employs soft-switching — and in data center PSUs, the LLC resonant converter has become the dominant topology precisely because it achieves this naturally. LLC converters achieve zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) on the secondary side within the resonant operating window, eliminating the overlap loss between voltage and current waveforms that dominates hard-switched converter losses.

GaN HEMTs are particularly well-matched to LLC topology because their lower output capacitance and gate charge — compared to silicon MOSFETs — results in lower driving loss and shorter dead times. A 2023 paper from the Institute of Microelectronics, Chinese Academy of Sciences confirmed that these properties enable ultra-high efficiency, high operating frequency, and compact converter size in the LLC topology, with soft-switching properties ensuring switches and diodes on the primary operate under ZVS/ZCS conditions. The University of Cassino and Southern Lazio’s 2021 state-of-the-art review explicitly identifies servers and telecom systems as target applications for GaN-based LLC converters, directly linking the technology to data center infrastructure requirements.

“GaN HEMTs’ lower output capacitance and gate charge results in lower driving loss and shorter dead times compared to silicon MOSFETs, enabling ultra-high efficiency, high operating frequency, and compact size in the LLC topology.”

Beyond LLC, the bidirectional CLLC topology has been validated for high-frequency GaN operation. South China University of Technology’s 2019 analysis reports a 400 W prototype with a maximum operating frequency exceeding 500 kHz, achieving 97.02% peak conversion efficiency in forward mode. The paper provides an improved ZVS condition incorporating parasitic parameters — a necessary refinement at high frequencies where parasitics interact strongly with the resonant tank and gate driver timing. This is not a minor detail: at 500 kHz, the gate driver’s dead-time accuracy becomes critical. Insufficient dead time prevents ZVS, while excessive dead time increases reverse conduction loss, as analysed by Czech Technical University in Prague in 2020.

Navitas Semiconductor’s 2020 active patent integrates gate driver intelligence directly with resonant converter control: the GaN power switch driver causes the switch to become non-conductive precisely when the current through it transitions across a threshold value, implementing zero-current detection to enforce soft switching. This closed-loop approach eliminates timing margin uncertainty that would otherwise force conservative — and lossy — dead-time settings in open-loop designs. Southeast University (China) extended this concept in a 2024 US patent: a DSP pre-stores a data table mapping load current to optimal gate driver voltage and pre-charge time, minimising the sum of switching loss, turn-on loss, and gate drive loss across the full load range encountered in data center PSUs. Standards bodies including IEC and efficiency programmes such as the 80 PLUS specification drive data center PSU designers toward the very efficiency levels these adaptive techniques target.

Monolithic Integration and Active Gate Driver Techniques

Parasitic inductance in the gate drive loop is the primary constraint on switching speed in discrete GaN implementations, and a source of ringing that re-introduces switching loss even in resonant converter topologies. Monolithic integration of the gate driver with the power GaN HEMT directly eliminates this constraint. Interuniversity Microelectronics Centre (IMEC) reported in 2019 that monolithic integration reduces switching time by 86% at turn-off and 45% at turn-on compared to discrete gate driver configurations at 100 V / 10 A operating conditions, with the improvement attributable directly to minimised parasitic inductance in the gate drive loop.

GaN Systems Inc. formalised the integration benefit in a 2016 US patent disclosing a monolithically integrated GaN driver comprising smaller E-Mode GaN HEMTs. One device provides gate drive voltage; another clamps the gate to source via an internal source-sense connection. Boosting drive voltage to the gate of the first device produces firm and rapid pull-up for improved switching performance at higher switching speeds. This architecture directly addresses the sub-10 ns switching transients characteristic of GaN devices, where any loop inductance in a discrete implementation causes voltage overshoot that either triggers false turn-on or forces the designer to slow the transition — reintroducing switching loss.

At higher bandwidths, IBM Research demonstrated a 6.7-GHz active gate driver for GaN FETs in 2018 capable of shaping the switching waveform during the transient itself. The programmable driver integrates high-speed memory, control logic, and parallel output stages to activate a near-arbitrary sequence of pull-up or pull-down resistances within a single switching event, enabling real-time control of dv/dt and di/dt to simultaneously reduce EMI and switching loss. Renesas Design (UK) Limited’s 2026 pending US patent pursues a production implementation of this principle: during the first portion of turn-on, a high pull-up resistance slows the initial dv/dt to limit EMI; during the second portion, a low pull-up resistance completes turn-on rapidly. An asymmetric resistance sequence during turn-off similarly uses low pull-down resistance initially, then high resistance as the gate approaches threshold, precisely controlling the tail of the switching transition. Research published by Nature Electronics and standards from ISO on wide-bandgap semiconductor reliability both underscore the importance of controlled dv/dt for long-term device robustness in mission-critical data center applications.

Chiba University demonstrated resonant gate driving at 7 MHz in 2018 using a class-E amplifier with an isolation transformer. By incorporating gate capacitance and resistance directly into the resonant filter, the driver achieves sinusoidal driving waveforms without distortion, with class-E zero-voltage switching and zero-derivative switching conditions minimising driver power consumption. The isolation transformer reduces destruction risk from high-voltage transients — a practical safety consideration in high-voltage GaN converters where primary-side gate drivers must be isolated from the control plane.

Key Patent Assignees and the Shape of the Innovation Landscape

The resonant gate driver patent landscape spans more than 50 documents from foundational circuit concepts (from as early as 1990) through current-generation GaN-specific implementations published up to 2026, with four overlapping technical areas: energy-recovery resonant gate drive topologies; soft-switching converter architectures (LLC, CLLC, ZVS, quasi-square-wave) that interact directly with driver design; monolithic and hybrid GaN integration strategies; and active and adaptive driver techniques for EMI management and efficiency optimisation.

Queen’s University at Kingston

Queen’s University at Kingston is the most prolific single assignee in the resonant gate drive circuit patent space, with at least six patents across US, CA, and WO jurisdictions. These cover full-bridge inductor-based energy recovery (2006), centre-tapped transformer variants (2007), and current source drivers with negative gate voltage capability (2012). The negative gate voltage capability is particularly relevant for GaN HEMTs with low threshold voltages, where ensuring a sufficiently negative off-state voltage prevents false turn-on under high dv/dt conditions — a failure mode that becomes increasingly likely as switching speeds increase toward the MHz range.

Koninklijke Philips Electronics / Signify Holding B.V.

Koninklijke Philips Electronics and its successor Signify Holding B.V. represent a continuous institutional lineage from Philips’ foundational resonant gate driver patents (2001–2002) through to Signify’s GaN-specific switch-mode driver circuits active in WO, EP, IN, JP, and CN jurisdictions (2022 and 2025). The Signify family addresses a GaN-specific practical issue: sensing components connected to the GaN switch can create voltage drops that disturb gate-source drive voltage stability during switching. The driver architecture synchronises the enabling of the sensing function with gate charge/discharge timing to prevent this disturbance.

General Electric Company

General Electric holds the foundational patents establishing series resonant and lossless gate driver architectures, from 1990 and 1991 through to the 2002 high-frequency resonant gate driver for MOS-gated power switches. These documents provide the conceptual foundation — series resonant energy transfer between gate capacitance and a storage capacitor, with timing circuitry ensuring proper sequencing — upon which all subsequent GaN-specific resonant driver designs build. According to WIPO patent records, GE’s foundational filings remain among the most-cited prior art in this technology area.

Navitas Semiconductor and Southeast University

Navitas Semiconductor contributes active GaN-specific resonant converter control patents integrating zero-current detection directly into the gate driver (2020), reflecting the trend toward intelligent gate drivers that adapt in real time rather than operating with fixed timing. Southeast University (China) extends this with fully adaptive DSP-controlled gate driver optimisation (2024 US patent): a DSP pre-stores a data table mapping load current to optimal gate driver voltage and pre-charge time, minimising the sum of switching loss, turn-on loss, and gate drive loss across the full load range. This adaptive approach is particularly relevant for data center PSUs, which must maintain high efficiency across a wide dynamic load range as server workloads fluctuate.

Academic and Research Institutions

Academic institutions — University of Cassino (Italy), South China University of Technology, IMEC (Belgium), Czech Technical University in Prague, and Chiba University (Japan) — are active contributors to GaN LLC/CLLC resonant converter and gate driver characterisation literature. IBM Research’s 2018 demonstration of a 6.7-GHz active gate driver represents the highest-bandwidth active waveform shaping result in the dataset, while Sungkyunkwan University’s 2019 charge-recycling IC provides the most direct quantification of gate drive loss reduction: 87.7% reduction with 90.3% peak power conversion efficiency in a 65 nm CMOS test chip. The U.S. Department of Energy‘s ongoing investment in wide-bandgap power electronics for data center efficiency further underscores the strategic importance of this technology area.