Why copper resistivity collapses below 10nm — and what ruthenium offers instead

Copper’s resistivity advantage over other metals disappears sharply once interconnect line widths fall below approximately 10nm. As line widths shrink below the electron mean free path of roughly 40nm in bulk copper, surface roughness scattering and grain-boundary scattering come to dominate electron transport, causing resistivity to rise polynomially rather than remaining near the bulk value of approximately 1.7 µΩ·cm. A 2025 Samsung Electronics patent filing explicitly cites the peer-reviewed finding that “for sub-10nm upper metal lines (i.e., upper metal lines with widths less than 100 angstroms), metals such as Ru, rhodium (Rh), and iridium (Ir) have lower resistivity than Cu,” referencing IEEE JEDS scaling data to support the claim.

The problem is compounded by the structural overhead of conventional copper diffusion barriers. Standard TaN/Ta bilayer stacks are required to prevent copper from migrating into surrounding low-k dielectric materials — a failure mode that causes device leakage and reliability loss. At sub-10nm trench widths, these barrier layers consume a disproportionate fraction of the available conductor cross-section, further increasing effective line resistance even before scattering effects are considered. TSMC’s 2022 patent on low-resistance copper interconnects addresses this directly, proposing the elimination or thinning of TaN and its replacement with a ruthenium diffusion barrier, and stating that ruthenium liners “may decrease the overall resistivity of the dual damascene structure” by reducing RC time constants and increasing signal propagation speed.

Electromigration reliability is a second, equally important axis. Copper atoms migrate along grain boundaries and at the Cu/dielectric interface under high current densities, gradually eroding conductor cross-sections and causing open-circuit failures. IBM’s 2022 patent on cobalt-injected ruthenium liners and cobalt cap layers confirms that “in 7nm technology and larger, ruthenium (Ru) liners are used for better copper (Cu) fill,” and describes how the combined cobalt-injected ruthenium liner and cobalt cap suppress the primary electromigration diffusion pathways. A SMIC Beijing patent (2024) adds that ruthenium’s strong oxidation resistance “can suppress the probability of copper electromigration, avoid the increase in copper conductor resistance, and affect the performance of the interconnect line,” while also noting that composite ruthenium-copper structures eliminate the need for a separate diffusion barrier layer entirely, enabling size reduction at the trench level.

“For sub-10nm upper metal lines, metals such as Ru, rhodium, and iridium have lower resistivity than Cu — a finding now explicitly cited in production-oriented patent filings from Samsung Electronics.”

Structural and process innovations enabling ruthenium BEOL integration

Deploying ruthenium in sub-10nm BEOL interconnects requires far more than substituting one metal for another — it demands a systematic rethinking of liner geometry, deposition chemistry, planarization, and barrier integration. The patent record documents four distinct structural approaches, each targeting a specific integration challenge.

Ultra-thin liner and bilayer stacks

The most widely documented near-term approach is the ruthenium liner: a thin conformal ruthenium film deposited inside a damascene trench before copper fill. Applied Materials’ 2025 patent on methods for forming metal liners specifies that the ruthenium layer in a BEOL liner stack can be deposited to a first thickness of approximately 5 angstroms or less — a deposition precision that demands atomic-layer-level process control. The complementary Applied Materials 2022 patent describes a bilayer architecture with a ruthenium layer and a cobalt layer on a barrier layer, where the ruthenium provides the copper seed interface and the cobalt caps the filled copper line, simultaneously addressing adhesion, barrier performance, and electromigration cap requirements.

TSMC’s 2024 patent on a ruthenium-based liner for copper interconnects describes a via process where a ruthenium-based liner is deposited inside a via followed by a copper plug, with the ruthenium material reducing the “pinch point at a top portion of the via” and improving copper deposition quality. A 2025 TSMC patent on interconnect structure formation goes further, describing selective deposition of a TaN barrier layer on sidewalls of openings while excluding exposed ruthenium via surfaces, then depositing a ruthenium-based liner with a bottom portion thicker than the sidewall portion — a geometry engineered to minimise contact resistance between the ruthenium liner and underlying ruthenium contact vias.

CMP compatibility through doping before planarization

Ruthenium is significantly harder and more chemically stable than copper, making it substantially more difficult to planarize using conventional chemical-mechanical planarization (CMP). Copper is soft and prone to dishing; ruthenium resists both the mechanical and chemical components of standard CMP slurries. TSMC’s 2025 patent on interconnect layer manufacturing and its 2021 patent on ion implantation procedures for defect repair in metal layer planarization describe a doping-before-polish approach: ruthenium metal is deposited to overfill openings, then doped — for example by ion implantation — and then polished. Doping modifies ruthenium’s CMP response, resolving one of the primary manufacturability obstacles to all-ruthenium interconnect layers. This process innovation is referenced in WIPO patent databases as a key differentiator for TSMC’s ruthenium integration roadmap.

Hybrid ruthenium–copper metallization layers

The near-term production architecture across multiple assignees is a hybrid: ruthenium for narrow lines, copper for wide lines, both within the same metallization level. Samsung’s 2025 patent filing describes this explicitly — narrow upper metal lines below 10nm use ruthenium, while wider lines use copper, with the choice validated by scaling data showing that Ru, Rh, and Ir outperform Cu at sub-10nm while Cu retains an advantage at wider pitches. Zhejiang Chuangxin Integrated Circuit’s 2026 patent formalises the threshold: interconnect lines with width ≤17nm use cobalt, ruthenium, or molybdenum as the primary conductor, while lines wider than 17nm continue to use copper, explicitly combining the advantages of each metal and improving both RC delay and electromigration performance in the BEOL stack.

Crystallographic control of ruthenium films

Samsung’s 2025 patent on interconnect structure and integrated circuit device specifies crystallographic requirements for advanced ruthenium films: a <001> crystal grain texturing factor F001 of approximately 0.7 to 1.0 and an average grain size of 50–200nm. This demonstrates that grain texture engineering — not just composition — is becoming a critical process control variable for ruthenium interconnect resistance optimisation. Grain boundary density directly affects electron scattering, so controlling crystallographic texture during deposition is essential to realising the theoretical resistivity advantage of ruthenium at sub-10nm dimensions. Samsung’s 2026 patent on ruthenium alloys extends this further, proposing ruthenium plus a first element at up to 40 atomic percent in a single-phase configuration, tuning resistivity and grain growth characteristics without introducing a second crystallographic phase that might scatter electrons.

Memory, logic, and 3D stacking: where ruthenium interconnects are being deployed

Ruthenium interconnects are being deployed across all three major BEOL application categories — logic, memory, and stacked 3D device architectures — with memory currently the most advanced in production deployment and 3D logic presenting the most demanding future requirements.

DRAM bit lines: ruthenium already in production

Samsung’s DRAM bit-line structures already use ruthenium wiring, making memory the application domain furthest along in ruthenium deployment. Samsung’s 2022 and 2025 patents describe DRAM bit-line structures where the wiring conductor is ruthenium, with graphene layers contacting the lower surface of the ruthenium wiring to further reduce resistance. This combination of a ruthenium conductor and a graphene interface layer represents an advanced approach to minimising bit-line RC delay in scaled DRAM. A separate Samsung 2025 patent introduces a dual-via architecture where a first ruthenium via contacts the metal layer and a reaction inhibitor, and a second ruthenium via with higher resistivity sits above it — suggesting engineered resistivity gradients within single interconnect vias for impedance management.

Logic BEOL: hybrid metallization at advanced nodes

In logic BEOL, the ruthenium-in-narrow-lines / copper-in-wide-lines hybrid architecture is the dominant approach across multiple assignees. Samsung’s 2024 Korean patent describes an IC device where narrower lower wiring omits a second metal pattern present in wider wiring, creating a selective metal scheme that targets resistance minimisation in critical nets. According to SIA roadmap data, resistance in local interconnects is one of the primary contributors to performance loss at advanced nodes, reinforcing the engineering rationale for selective metal assignment by line width.

Stacked 3D logic: thermally stable ruthenium–aluminum vias

Stacked transistor and next-generation 3D logic architectures impose an additional requirement on BEOL interconnects: thermal stability. In sequential 3D integration, the upper device tier is processed after the lower tier is complete, exposing existing interconnects to subsequent high-temperature fabrication steps. Copper and cobalt contacts degrade under these conditions. TSMC’s 2025 patent on device-level interconnects for stacked transistor structures describes source/drain vias comprising ruthenium and aluminum — as a ruthenium plug wrapped by an aluminum liner, as a ruthenium aluminide compound, or as a ruthenium plug wrapped by a ruthenium aluminide liner. The high thermal stability of these ruthenium-based vias is emphasised as essential for stacked device processing. This extends ruthenium’s BEOL role from purely electrical performance optimisation into process thermal budget management for future device architectures.

Tokyo Electron’s 2023 patent on interconnection structure and method of formation discloses a barrier-free or reduced-barrier approach: a first metal is conformally filled in damascene openings in direct contact with the dielectric material, with a second metal encapsulated by the first metal. This approach is enabled by ruthenium’s inherent resistance to copper diffusion and its compatibility with low-k dielectrics, as tracked in the EPO patent database under advanced BEOL metallization classifications. GlobalFoundries’ early work (2014 and 2020 patents) documented the galvanic corrosion problem that arises when ruthenium and copper are in contact and exposed — copper recessing below the plane of the ruthenium-coated dielectric, with a cap layer filling the recess — establishing the manufacturability foundations that later foundry entrants have built upon.

The patent landscape: dominant players, diverging strategies, and the global scale of the transition

The patent corpus for sub-10nm ruthenium BEOL interconnects spans filings from approximately 2002 to 2026, with the most technologically relevant disclosures concentrated between 2020 and 2026. The dominant assignees are TSMC, Samsung Electronics, Applied Materials, IBM, and GlobalFoundries, with Chinese foundries including SMIC Beijing, Shanghai Huali, and Zhejiang Chuangxin Integrated Circuit reflecting the global scale of this transition.

TSMC: systematic coverage of the full integration flow

TSMC is the most prolific assignee in the relevant dataset, with filings spanning ruthenium liners for copper vias, doped ruthenium CMP processes, ruthenium–aluminum vias for stacked transistors, and selective TaN/Ru barrier integration. TSMC’s filings are notable for their systematic coverage of the full integration flow, from liner deposition chemistry to CMP defect repair. The 2021 and 2025 CMP patents in particular reflect a multi-year engineering programme to solve ruthenium’s planarization challenges, while the 2025 stacked transistor via patent extends TSMC’s ruthenium IP into the 3D integration domain. TSMC’s patent strategy, tracked in the PatSnap Insights database, reflects a deliberate approach to building freedom-to-operate across the entire ruthenium BEOL value chain.

Samsung: memory deployment ahead of logic, with crystallographic innovation

Samsung Electronics is the second most prominent assignee and appears to be further along in deploying ruthenium in production memory devices. Samsung’s patents cover DRAM bit-line ruthenium wiring with graphene interfaces, dual-via resistivity-gradient structures, hybrid ruthenium/copper logic BEOL, and crystallographic control of ruthenium film texture. The 2025 patent specifying a <001> crystal grain texturing factor F001 of approximately 0.7 to 1.0 and average grain size of 50–200nm is particularly significant: it signals that Samsung is moving beyond composition control to microstructure engineering as the primary lever for resistance optimisation.

Applied Materials: process equipment defining liner stack specifications

Applied Materials holds a critical position in the deposition equipment and process side, with patents on ruthenium/cobalt bilayer liner formation processes that are likely used by multiple foundry customers. Their specifications — ruthenium deposited to approximately 5 angstroms or less, cobalt cap to less than 20 angstroms — define process-node-critical liner stack parameters that foundries must match to achieve the resistance and reliability targets documented in their own patent filings. This equipment-level IP creates a significant dependency for any foundry seeking to deploy ruthenium BEOL at scale. The PatSnap IP landscape analysis tool enables R&D teams to map these cross-dependency relationships systematically.

IBM: foundational materials science and longer-horizon alternatives

IBM contributes foundational materials innovation, particularly the cobalt-injected ruthenium liner concept (2022) and transition-metal patterned sub-80nm-pitch conductive lines (2017). IBM also explores topological semimetal interconnects as a longer-horizon alternative, filed in 2023, indicating that IBM’s interconnect research extends beyond the current ruthenium transition to post-ruthenium material candidates. This dual-track approach — optimising current-generation ruthenium structures while investigating next-generation alternatives — is consistent with IBM’s historical role as a materials research leader in semiconductor interconnects.

Chinese foundries: closing the gap

SMIC Beijing, Shanghai Huali, and Zhejiang Chuangxin Integrated Circuit are filing increasingly detailed ruthenium BEOL patents, indicating active development programs aimed at sub-10nm production readiness. The Zhejiang Chuangxin 2026 patent explicitly codifying the ≤17nm / >17nm threshold for metal selection is notable for its specificity — it reflects engineering data rather than exploratory claims, suggesting the company has conducted sufficient process development to define quantitative design rules for hybrid ruthenium–copper metallization.

“Ruthenium’s role in BEOL is expanding from liner to standalone conductor to thermally stable 3D via — each step documented in patents that collectively map the full displacement of copper at sub-10nm nodes.”