Samsung vs TSMC: 5nm to 2nm process roadmap showdown

FinFET Maturity and the 5nm Inflection Point

At the 5nm node, both Samsung and TSMC pushed FinFET architecture to its practical limits using EUV lithography — but their patent filings reveal meaningfully different engineering philosophies. TSMC’s 5nm work, evidenced in patents reviewed by PatSnap’s innovation intelligence platform, centred on advanced gate replacement processes for improved bottom coverage in FinFETs, epitaxial growth using {110} crystallographic orientation to reduce defects and parasitic capacitance, and pulsed-bias etching with annealing to improve fin crystallinity and reduce surface roughness.

Samsung’s 5nm patent strategy took a different path: diamond-like gate structures with (111) crystallographic orientation for enhanced carrier mobility, omega-gate structures with reduced-width stem regions for improved gate control, and fin cutting processes with high band-gap insulating liners to address leakage. These divergent approaches — TSMC optimising for process uniformity and defect reduction, Samsung experimenting with novel gate geometries — foreshadowed the more dramatic architectural split that would emerge at 3nm.

According to WIPO patent filing trends, semiconductor process patents have been among the fastest-growing categories in global IP filings over the past decade, with EUV-related filings accelerating sharply after 2018. The 5nm generation represented the last node at which both companies shared the same fundamental transistor architecture before their paths diverged.

The GAA Transition Divergence: Samsung Bets Early, TSMC Waits

Samsung became the first foundry in the world to implement Gate-All-Around (GAA) technology at the 3nm node in June 2022, while TSMC deliberately maintained FinFET architecture at its own 3nm node launched in September 2022, deferring GAA to 2nm. This single strategic decision is the defining fork in the Samsung vs. TSMC semiconductor process technology roadmap.

Samsung’s claimed performance metrics for its 3nm GAA node were substantial: a 45% area reduction versus 7nm FinFET, 50% lower power consumption, and a 35% performance improvement. Patent evidence supports the depth of Samsung’s GAA R&D investment — filings cover variable nanosheet width and count for optimised on-current and reduced off-current, contact isolation architecture for time-dependent dielectric breakdown (TDDB) and power efficiency, and 3D-stacked Complementary FET (CFET) designs with vertical integration of p-type and n-type GAA FETs.

“Samsung became the first foundry to implement GAA technology at 3nm in June 2022 — but industry feedback on market reception was lower than expected, with yield and client adoption challenges noted.”

TSMC’s counter-strategy at 3nm was characterised by discipline rather than caution. By locking in Apple, NVIDIA, Qualcomm, and MediaTek for bulk 3nm FinFET capacity, TSMC secured revenue and production experience while simultaneously filing GAA preparation patents — nanosheet structures with varying channel widths for multi-VT operation, modulated nanosheet dimensions for high-speed/low-power optimisation, and silicide contact structures to reduce parasitic resistance. TSMC was not ignoring GAA; it was staging its transition to avoid the yield exposure Samsung encountered.

The 2nm Node Race: Convergence on GAA and Backside Power

At 2nm, the Samsung vs. TSMC semiconductor process technology roadmap converges on the same fundamental architecture — GAA nanosheets with backside power delivery (BSPD) — but the two companies arrive at this destination with very different histories, client books, and execution risks.

Samsung’s 2nm advantage is the roughly 12-month GAA production experience it accumulated at 3nm — a lead that could prove decisive if TSMC encounters unexpected yield challenges during its own FinFET-to-GAA transition. Samsung has already secured its first 2nm AI chip order from Japan’s Preferred Networks, signalling that its early-access strategy is attracting at least some clients willing to accept production risk in exchange for early availability.

TSMC’s 2nm challenge is the opposite of Samsung’s: it must execute a simultaneous node shrink and transistor architecture change, moving from FinFET at 3nm to GAA at 2nm. Rumors reported by Tom’s Hardware suggest 2nm mass production may shift from early 2025 to late 2025 or 2026 due to construction pace and demand calibration, though TSMC has publicly stated that “factory construction is progressing according to plan.” According to standards bodies including IEEE, the transition from FinFET to GAA represents one of the most significant transistor architecture shifts since the introduction of FinFET itself in the early 2010s.

Advanced R&D Frontiers: What Patent Filings Reveal

Patent filings from both companies — covering more than 49 TSMC patents and 50+ Samsung and multi-source GAA patents in the analysis scope — identify three shared technical frontiers that will define semiconductor process capability beyond 2nm: nanosheet optimisation, selective etching for nanosheet release, and Complementary FET (CFET) integration.

GAA Nanosheet Optimisation

Both companies are filing patents on inner spacer width reduction to minimise capacitance, vertically stacked channel structures with varying thicknesses to address short-channel effects, and L-shaped active regions for shrinking feature sizes and power savings. These are not incremental improvements — they represent the core engineering work required to sustain scaling beyond 2nm, as noted in process technology assessments published by Nature Electronics and related journals.

Selective Etching for Nanosheet Release

One of the most technically demanding steps in GAA fabrication is selectively removing the SiGe sacrificial layers to release the Si nanosheet channels without damaging the surrounding structure. Patent filings reveal two competing approaches: plasma-based lateral etching with passivation and etch phase control achieving SiGe-to-Si selectivity greater than 150:1, and gas-phase selective etching using fluorine-containing interhalogen gases. Both methods target the same >150:1 selectivity threshold, suggesting this is an industry-wide benchmark for acceptable nanosheet release quality.

Samsung-Specific: CFET and 1.4nm Roadmap

Samsung’s patent portfolio shows particular depth in Complementary FET (CFET) technology — vertical stacking of p-type and n-type GAA FETs with buried metal layers for power distribution, and multi-stack nanosheet architectures with independent work-function metal control for upper and lower transistors. For its 1.4nm node (targeted at 2027), Samsung is pursuing a fourth nanosheet addition to increase drive current and reduce leakage, along with enhanced thermal management through improved current control.

TSMC-Specific: Application-Tuned Nanosheet Dimensions

TSMC’s GAA preparation patents emphasise application-specific tuning: nanosheet width and spacing modulation for high-speed versus low-power optimisation, integrated GAA nanowire and nanosheet devices with varying channel widths on the same die, and silicide contact structures to minimise parasitic resistance in source and drain regions. This application-tuned approach reflects TSMC’s need to serve an unusually diverse client base spanning mobile, HPC, automotive, and AI workloads — a portfolio challenge that OECD semiconductor industry analyses have identified as a key driver of foundry R&D complexity.

Capital Commitments and Strategic Positioning Through 2026

The Samsung vs. TSMC semiconductor process technology roadmap is ultimately a contest between two different theories of competitive advantage — and those theories are backed by capital commitments of a scale that few industries can match.

TSMC committed $100 billion between 2021 and 2024 for global expansion, including new fabs in the United States and Japan. This investment is concentrated on securing the supply chain relationships and geopolitical positioning that underpin its client ecosystem. Apple, NVIDIA, Qualcomm, MediaTek, Broadcom, and Intel have all pre-booked 2nm capacity, creating a demand floor that de-risks TSMC’s capital expenditure even if the node ramp is slower than planned.

Samsung has committed $150 billion by 2030 for system semiconductors, including a $17 billion Texas fab that became operational in late 2023. Samsung’s foundry client base of approximately 100 clients is narrower than TSMC’s, but the company’s early-access strategy — offering risk production at leading-edge nodes to attract clients who want to influence product roadmaps — is designed to convert technology leadership into commercial relationships before TSMC’s ecosystem lock-in becomes permanent.

“TSMC’s 2nm leadership is anchored on ecosystem lock-in and volume execution, not pure technology timing. Samsung’s GAA-first strategy creates a narrow window in 2025–2026 to prove production maturity and convert early access into market share gains.”

The 2025–2026 period is therefore a genuine inflection point. Samsung must demonstrate stable 2nm GAA yield to convert early access into volume orders, win flagship design-ins from clients such as NVIDIA, Tesla, or Apple, and leverage its 12-month GAA experience to derisk TSMC’s transition challenges. TSMC, meanwhile, must execute its first-ever GAA node at commercial scale while managing potential schedule adjustments and maintaining the yield reputation that underpins its premium pricing. The Semiconductor Industry Association has noted that advanced node transitions of this complexity typically take 18–24 months to reach full production yield maturity.