From foundational phase to commercial scale: the SiC epitaxy innovation timeline
SiC epitaxial growth has evolved through three distinct phases since the mid-1990s, each visible in the patent record. The earliest SiC-specific epitaxial patents date to 1996, anchored by Cree Research’s liquid phase epitaxy work on defect reduction and Northrop Grumman’s a-axis growth methods — both focused on achieving any viable growth on SiC substrates at all. That foundational question has long been answered; the field has since moved to answering a harder one: how to grow with sufficient uniformity, throughput, and defect control to serve high-volume power device manufacturing.
A second wave of filings from approximately 2004–2011 reflects the commercialisation phase. Sumitomo Electric Industries filed multiple CVD uniformity patents in Japan between 2004 and 2010; Mississippi State University disclosed halogenated carbon precursor methods in US and EP jurisdictions from 2007–2008; and Toyota Motor Corporation addressed low C/Si ratio growth for defect-free thin films in Japan in 2008. The defining feature of this era was yield: researchers and process engineers were no longer just growing SiC epitaxial films — they were trying to grow them with enough consistency to ship product.
The most recent filings, spanning 2021–2026, signal a maturation and scale-up phase characterised by reactor hardware innovation, multi-jurisdictional IP capture, and entry into adjacent application domains. Mitsubishi Electric Corporation’s tantalum carbide susceptor system (US 2021, US 2025), Toshiba Electronic Devices & Storage Corporation’s two-rate growth architecture (US 2025), and Hitachi Energy Ltd’s dopant-enriched substrate preparation method (EP 2026) all represent incremental but commercially significant process refinements. According to WIPO filing trends, sustained multi-year patent activity across a technology cluster of this type indicates active commercial deployment rather than exploratory research.
This landscape is derived from a targeted set of patent and literature records retrieved across focused searches. It represents a snapshot of innovation signals within this dataset only and should not be interpreted as a comprehensive view of the full industry. Publication dates in the dataset span 1996 to 2026, with the heaviest cluster between 2013 and 2025.
Four growth approaches, one dominant path — and its limits
Hot-wall CVD with chlorinated precursors is the dominant commercial SiC epitaxial growth route, and the patent record confirms it: this approach is the most heavily represented in the dataset. Chlorinated silicon precursors — dichlorosilane (SiH₂Cl₂), trichlorosilane, and silicon tetrachloride — suppress silicon cluster formation at high temperatures, enabling growth rates of 30–100 μm/h versus the 5–20 μm/h achievable with conventional silane-based CVD. This throughput advantage is the decisive factor for cost-competitive power wafer production. As tracked by IEEE, chlorinated CVD has become the reference process in SiC power device research publications over the past decade.
Hot-wall CVD using chlorinated silicon precursors such as dichlorosilane achieves SiC epitaxial growth rates of 30–100 μm/h, compared to 5–20 μm/h for conventional silane-based CVD processes, as demonstrated on 8° off-axis 4H-SiC substrates with RMS roughness of 0.5–2.0 nm and doping below 1×10¹⁴ cm⁻³.
Within CVD, the key process variables are the C/Si ratio (typically 0.5–1.8 in this dataset), growth temperature (most commonly 1550°C–1700°C), carrier gas chemistry, pressure, and substrate off-angle. Off-angles of 4° and 8° from the (0001) basal plane are the most frequently referenced; a documented trend toward lower off-angles (≤4°) reflects the industry’s push to reduce substrate waste. Resonac Corporation’s 2017 JP patent controls C/Si ratio in the range of 1.0–2.0 and a pressure-times-growth-rate product of 45–100 kPa·μm/hr to achieve in-plane doping uniformity. A 2023 literature study quantified morphology and defect evolution across C/Si ratios of 1.0–1.2 and temperatures of 1570–1630°C, achieving RMS roughness as low as approximately 0.186 nm at optimised conditions.
“Chlorinated precursor chemistry is the de facto standard for high-throughput CVD — dichlorosilane and trichlorosilane-based processes appear in both patent filings and academic literature as the dominant path to growth rates greater than 30 μm/h.”
Sublimation epitaxy: the thick-layer alternative
Sublimation epitaxy — derived from the modified Lely method — uses a polycrystalline SiC source and a monocrystalline SiC seed in a closed crucible. Kiselkarbid i Stockholm AB dominates this sub-field in the dataset, having filed across six jurisdictions on a core innovation: a carbon getter with a melting point above 2200°C, placed within the crucible to bind carbon species evaporated from the SiC source, suppressing carbon inclusions and basal plane dislocations. The reported growth rate range spans 1 μm/h to 1 mm/h — the upper end of this range makes sublimation uniquely suited to producing the 100–200 μm thick epitaxial layers required for ultra-high voltage devices rated above 10 kV.
Liquid phase epitaxy and heteroepitaxial routes
Liquid phase epitaxy (LPE) using silicon-rich melts represents a lower-temperature alternative to CVD. Toyo Tanso Co., Ltd. is the primary driver of LPE innovation in this dataset, with at least six filings across US and EP jurisdictions covering seed materials, feed material architectures, and growth units. A separate heteroepitaxial strand — growing 3C-SiC on (001) silicon substrates — has attracted filings from the University of Warwick (US, 2021) and earlier work from Commissariat a l’Energie Atomique, targeting MEMS and photonic integration where silicon-compatible processes are required. According to standards bodies such as ISO, MEMS process compatibility with silicon fabrication lines remains a significant commercial driver for heteroepitaxial SiC development.
Virtually every active filing in this dataset targets basal plane dislocation (BPD) density, stacking fault density, or surface morphology defect counts. Commercial benchmarks from Resonac Corporation, Fuji Electric, and Mitsubishi Electric require BPD densities below 10/cm², stacking fault densities below 10/cm², and doping uniformity within ±5% across the wafer. Teams entering this space must demonstrate BPD-to-TED conversion rates above 99% and surface defect density at or below 1/cm² to compete.
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Analyse SiC Patents in PatSnap Eureka →Assignee landscape: where SiC epitaxy IP is concentrated
Three assignees — Resonac Corporation, Kiselkarbid i Stockholm AB, and Toyo Tanso Co., Ltd. — account for the majority of retrieved filings in this dataset, but the range of jurisdictions and institution types signals that the competitive field is globally distributed rather than monopolised. Japan-origin innovation concentrates on CVD process refinement; Swedish innovation on sublimation; and US academic and government filings focus on defect reduction mechanisms and emerging platform applications.
In the SiC epitaxial growth patent dataset analysed here, Resonac Corporation (formerly Showa Denko K.K.) holds 9+ filings across JP, US, and EP jurisdictions; Kiselkarbid i Stockholm AB holds 8+ filings across US, EP, WO, AU, CA, IN, and SE; and Toyo Tanso Co., Ltd. holds 7+ filings across US and EP. The US leads all jurisdictions with approximately 30+ filings.
Resonac Corporation’s dominance reflects a deliberate CVD process optimisation strategy: its filings span step bunching suppression, doping uniformity, pre-growth etching protocols, and post-growth cooling methods. The majority of Resonac’s recent filings target the JP and US jurisdictions, consistent with its role as a tier-1 supplier to Japanese and global power device manufacturers. Kiselkarbid i Stockholm AB has taken the opposite approach — fewer core patents, but aggressive multi-jurisdictional coverage across seven jurisdictions (EP 2022, AU/CA/IN 2023, US 2024, SE 2024), signalling active commercialisation and creating substantial freedom-to-operate exposure in the sublimation epitaxy segment, as documented in its production-of-SiC-epitaxial-wafers filing (SE, 2024) which explicitly targets automotive electronics and power management in EVs.
Application domains driving SiC epitaxial wafer demand
Power semiconductor devices — MOSFETs, Schottky diodes, bipolar junction transistors, and IGBTs — represent the overwhelming majority of target applications in the retrieved patent set. The 4H-SiC polytype is universally preferred for power applications due to its wide bandgap of approximately 3.26 eV, high electron mobility, and ability to sustain high operating temperatures and breakdown voltages above 10 kV. As noted by OECD research on clean energy transition materials, SiC power devices are a critical enabler for the efficiency gains required in grid-scale renewable energy conversion and EV powertrains.
Commercial SiC epitaxial wafer benchmarks for power device applications require basal plane dislocation (BPD) densities below 10 per cm², stacking fault densities below 10 per cm², and doping uniformity within ±5% across the wafer. LX Semicon Co., Ltd.’s dual-rate growth architecture achieves a surface defect density at or below 1 per cm².
Electric vehicles and automotive electronics constitute a specifically named use case in Kiselkarbid i Stockholm AB’s 2024 SE filing on SiC epitaxial wafer production, alongside power grids and computer power supplies. The 200 mm wafer compatibility work is directly motivated by EV-scale cost reduction requirements: a 200 mm wafer roughly doubles the die area available per substrate relative to 150 mm, which translates directly into die cost reduction for the inverter MOSFETs used in EV traction drives. The LPE/REACTION project’s 2022 publication on its PE108 reactor — demonstrating run-to-run thickness variation below 1.4% and doping variation below 5.6% on 200 mm substrates — represents the current state of the art for large-diameter SiC epitaxy.
Beyond power electronics, two emerging application domains are visible in the most recent filings. Resonac Corporation’s 2019 US patent on epitaxial growth methods explicitly targets high-frequency, high-voltage resistant electronic devices, including RF transistors. More distinctively, Hewlett Packard Enterprise’s 2025 US filing describes a SiC-on-silicon platform targeting photonic integrated circuits, including the bonding of III-V semiconductor layers to SiC epitaxial layers grown on silicon-on-insulator substrates — a fundamentally different use case that extends SiC epitaxy into the datacentre photonics supply chain.
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Monitor SiC IP in PatSnap Eureka →Five emerging directions reshaping the SiC epitaxy frontier
The 2021–2026 filing cohort in this dataset is not a continuation of prior trends — it represents a set of structurally distinct technical bets, several of which converge on the same problem from different angles. Understanding these directions is essential for R&D teams and IP strategists positioning in SiC epitaxy.
1. Large-diameter (200 mm) uniform epitaxy
The 2022 literature report on the PE108 reactor documents the push to 200 mm SiC epitaxy as a cost-reduction imperative for EV-scale manufacturing. Multi-zone injection and tunable gas delivery configurations are the enabling hardware innovations. The concentration of 2024–2026 patent filings on reactor hardware — including Mitsubishi Electric Corporation’s tantalum carbide susceptor system and induction-heated rotating wafer holder — confirms that reactor design is the primary differentiation layer for 200 mm capability.
2. Two-stage growth rate architectures
Toshiba Electronic Devices & Storage Corporation’s 2025 US filing defines a two-rate paradigm: a low-rate nucleation layer at 0.5–2 μm/h producing a layer 1–100 nm thick, followed by a high-rate bulk growth layer above 2 μm/h producing the functional 4–100 μm thick epilayer. The low-rate stage seeds the surface defect landscape before the high-throughput bulk growth begins, decoupling defect nucleation from productive deposition. This paradigm is independently validated in LX Semicon’s earlier filings (2015–2016) and Resonac’s JP filings (2018), representing convergent industrial validation across three geographically distinct assignees.
3. Heteroepitaxial SiC on silicon
Two distinct approaches are emerging: 3C-SiC on (001) silicon for MEMS and photonics, documented in the University of Warwick’s cold-wall CVD method (US 2021) and independent stress-free bulk 3C-SiC growth reports from 2019; and SiC-on-insulator (SiCOI) composite substrates for RF and photonic integration, with Commissariat a l’Energie Atomique active in this space from US 2006 and JP 2005 filings. Hewlett Packard Enterprise’s 2025 photonic platform patent signals that this sub-field is entering a commercialisation phase, with only a handful of players in the dataset and correspondingly broad white space available.
4. Dopant-profile engineering at the substrate level
Hitachi Energy Ltd’s January 2026 EP filing introduces pre-growth substrate annealing in a dopant-matched gas atmosphere to create an enriched surface growth region. This is a fundamentally new substrate preparation paradigm distinct from conventional hydrogen etching — the approach modifies the substrate’s dopant concentration profile before epitaxial growth begins, rather than optimising the growth process itself. As the most recent filing in the dataset by publication date, it represents the current frontier of substrate-level innovation.
5. SiC as a graphene substrate platform
Literature records from 2011–2016 document the maturation of epitaxial graphene on SiC via confinement-controlled sublimation (CCS), originating from Georgia Tech research. The 2016 life-cycle assessment of epitaxial graphene production found that industrial-scale production is constrained primarily by SiC wafer energy costs rather than by the graphene growth process itself — a finding that creates a direct dependency between SiC epitaxy cost trajectories and the commercial viability of graphene-based devices.
Toshiba Electronic Devices & Storage Corporation’s 2025 US patent defines a two-stage SiC epitaxial growth architecture: a low-rate nucleation layer grown at 0.5–2 μm/h to a thickness of 1–100 nm, followed by a high-rate bulk layer grown above 2 μm/h to a final thickness of 4–100 μm, independently validated by LX Semicon and Resonac Corporation in prior filings.