What SPADs are and why they matter now
A Single Photon Avalanche Diode is a reverse-biased p-n junction photodetector operated above its breakdown voltage — a condition called Geiger mode — in which a single absorbed photon triggers a self-sustaining avalanche of charge carriers, producing a macroscopic detectable current pulse with picosecond-level timing resolution. That combination of single-photon sensitivity and sub-nanosecond timing is what makes SPADs foundational to applications ranging from automotive LiDAR and quantum key distribution to fluorescence lifetime imaging and space astronomy.
Key performance metrics tracked across the dataset include photon detection efficiency (PDE/PDP), dark count rate (DCR), timing jitter (FWHM), afterpulsing probability, and fill factor. These five parameters define the trade-off space that every SPAD design team must navigate — and no single device architecture currently optimises all five simultaneously. The dataset spans foundational silicon CMOS implementations through advanced III-V compound semiconductor structures and emerging 2D material platforms, covering device geometries from single-pixel discrete detectors to megapixel focal plane arrays.
Operating a SPAD in Geiger mode means biasing the p-n junction above its breakdown voltage (excess bias). A single photo-generated carrier is sufficient to trigger a macroscopic, detectable current pulse. The device must then be actively or passively quenched — returned below breakdown — before it can detect the next photon. Quenching and reset circuit design is a co-equal engineering challenge alongside the diode structure itself.
Circuit integration — particularly quenching and reset circuits — is highlighted across multiple retrieved results as a co-equal design challenge alongside the diode structure itself. This means SPAD IP is not confined to device patents: a substantial portion of the competitive moat lies in the readout architecture, as demonstrated by STMicroelectronics’ body-biasing approach in 28 nm FD-SOI that enables avalanche detection in under 40 ps. According to WIPO trend data, semiconductor photodetector patent filings have grown consistently over the past decade, with single-photon detection representing one of the fastest-expanding sub-categories.
A Single Photon Avalanche Diode (SPAD) is a semiconductor p-n junction photodetector biased above its breakdown voltage in Geiger mode, enabling detection of individual photons with picosecond-level timing resolution. Key performance metrics include photon detection efficiency (PDE), dark count rate (DCR), timing jitter (FWHM), afterpulsing probability, and fill factor.
Three eras of SPAD innovation: from p-n junctions to 28 nm FD-SOI
SPAD innovation divides into three discernible epochs based on publication dates across 80+ retrieved records, with each era defined by the dominant engineering constraint of its time.
The foundational era (pre-2008) established the basic physics. Early avalanche photodiode patents from Varian Associates (1974, US), Hitachi Ltd. (1974–1979, DE), and Thomson-CSF (1979, FR) established basic p-n junction avalanche multiplication principles. Politecnico di Milano’s monolithic active quench and reset circuit (2006, DE) marked the beginning of integrated readout architectures. The University of Geneva demonstrated free-running InGaAs/InP SPAD operation with ASIC-based active quenching as early as 2007, achieving 10% detection efficiency at less than 2 kHz noise in free-running mode — a foundational result for fiber-optic quantum key distribution.
The CMOS integration era (2008–2019) was defined by the drive to make SPADs manufacturable at scale. Standard CMOS compatibility became the dominant design goal, with results from institutions spanning 130 nm, 150 nm, 180 nm, and 350 nm nodes. INFN Laboratori Nazionali del Sud pioneered large bidimensional SPAD arrays in 2008. Hewlett Packard Labs demonstrated zero-change 0.18 μm CMOS SPAD integration for LiDAR in 2019, explicitly targeting cost and voltage minimisation with a breakdown voltage below 10 V. The EPFL AQUA group’s comprehensive biophotonics SPAD imager review (2019) signalled maturity of the platform for life sciences.
The optimization and scaling era (2020–present) is characterised by aggressive pixel pitch reduction, advanced node migration, and 3D integration. Approximately 60% of patent filings with active legal status in this dataset were published after 2019, confirming accelerating commercialization. Sony Semiconductor Solutions demonstrated a 3.06 μm pixel-pitch SPAD with 57% PDE and deep trench isolation in 2023. STMicroelectronics filed active SPAD patents for 28 nm FD-SOI technology in 2021 and avalanche pixel control circuits in 2024–2025.
“Approximately 60% of patent filings with active legal status in the SPAD dataset were published after 2019 — confirming that the technology has crossed from research into aggressive commercial deployment.”
Approximately 60% of SPAD patent filings with active legal status in the PatSnap dataset were published after 2019, indicating that the majority of commercially relevant SPAD intellectual property has been created during the optimization and scaling era from 2020 to the present.
Map the full SPAD patent landscape — assignees, claim clusters, filing timelines — in PatSnap Eureka.
Explore SPAD Patent Data in PatSnap Eureka →Four technology clusters shaping the competitive landscape
The SPAD patent and literature dataset organises into four distinct technology clusters, each addressing a different segment of the performance-cost-wavelength trade-off space. Understanding which cluster a given device architecture belongs to is the first step in competitive positioning.
Cluster 1: Standard CMOS-integrated silicon SPADs
The largest cluster centres on SPADs implemented in unmodified or minimally modified commercial CMOS processes. This approach trades some photonic performance for dramatic cost reductions and scalability. ICube/University of Strasbourg characterised eight diameter variants (5–40 μm) in 180 nm CIS technology, achieving DCR below 10 kHz at 15°C, 0.2% afterpulsing, and approximately 20% PDE. Université de Sherbrooke demonstrated 7.8 ps FWHM single-photon timing resolution at the 65 nm node by co-optimising the quenching circuit threshold and SPAD excess voltage — a result that sets the benchmark for time-resolved applications in standard CMOS. STMicroelectronics’ body-biasing approach in 28 nm FD-SOI enables avalanche detection in under 40 ps and halves afterpulsing charge, as reported by IEEE-published researchers in 2021.
Cluster 2: Enhanced-architecture SPADs for NIR and extended spectral range
Standard silicon SPADs have poor absorption efficiency beyond 800 nm — a fundamental materials limitation. Vrije Universiteit Brussel’s Current-Assisted SPAD (CASPAD) uses a 40×40×14 μm³ absorption volume with a majority-current-induced drift field directing photo-electrons toward a small central avalanche junction, achieving NIR operation at 785 nm in standard 350 nm CMOS. imec’s near-infrared enhanced silicon SPAD uses a ~15×15×18 μm³ depletion volume in customised 0.13 μm CMOS, achieving 13% PDE at 905 nm with less than 0.1% afterpulsing. University of Wisconsin-Madison’s diffractive nanostructure approach couples incident NIR photons into horizontal waveguide modes, achieving a 2.5× PDE improvement while maintaining thin-junction timing jitter.
Both the CASPAD (Vrije Universiteit Brussel/imec) and photon-trapping nanostructure approaches are actively competing to solve NIR detection in standard CMOS. Organisations that secure strong IP on drift-field-assisted or nanostructure-enhanced silicon SPADs at 850–1000 nm will capture the autonomous vehicle and industrial sensing segments without requiring III-V manufacturing.
Cluster 3: III-V and heterogeneous material SPADs for infrared and UV
Where silicon’s bandgap prevents operation at telecom wavelengths (1310/1550 nm), III-V compound semiconductors are required. University of Sheffield demonstrated 26% PDE at 1550 nm at 210 K with 70 ps timing jitter using InGaAs/InAlAs, showing the InAlAs avalanche region advantage over InP for reduced afterpulsing. University of Glasgow achieved 38% single-photon detection efficiency at 1310 nm at 125 K with a planar Ge-on-Si SPAD, delivering a 50× improvement in noise equivalent power versus mesa geometry and significantly reduced afterpulsing compared to InGaAs/InP. University of Sheffield’s 2023 work on antimony-based III-V quaternary materials demonstrates ionization ratios competitive with silicon, enabling low-noise SWIR APD/SPAD operation.
Cluster 4: SPAD arrays and pixel-level integration
This cluster addresses the scaling of individual SPAD cells into large-format arrays. Sony Semiconductor Solutions’ 3.06 μm SPAD pixel achieves 57% PDE, 0.4% crosstalk, and 15.8 counts-per-second DCR using two-step deep trench isolation and an embedded metal optical shield. Fondazione Bruno Kessler’s NUV-HD Silicon Photomultiplier achieves 63% PDE at 420 nm, 100 kHz/mm² DCR, and 100 ps coincidence resolving time in PET scintillator readout. Southwest Institute of Technical Physics fabricated 64×64 Si SPAD and InGaAsP/InP SPAD arrays for driverless vehicle LiDAR platforms.
Sony Semiconductor Solutions demonstrated a 3.06 μm pixel-pitch SPAD in 2023 achieving 57% photon detection efficiency, 0.4% optical crosstalk, and 15.8 counts-per-second dark count rate, using two-step deep trench isolation and an embedded metal optical shield — the smallest demonstrated SPAD pixel pitch in this dataset.
Application domains driving commercialization
Automotive LiDAR is the most commercially active application domain in this dataset, with multiple records explicitly citing LiDAR as the primary design driver. However, the application landscape is broad and each vertical demands a distinct device parameter trade-off.
Automotive LiDAR and 3D ranging
SPAD-based time-of-flight systems directly enable autonomous vehicle sensing. Hewlett Packard Labs’ P+/N-well junction SPAD in 0.18 μm CMOS achieves a breakdown voltage below 10 V, explicitly targeting cost and voltage minimisation for LiDAR. Southwest Institute of Technical Physics deployed 64×64 array-format SPADs in driverless vehicle LADAR platforms. The Tip Avalanche Photodiode from KETEK GmbH (2021) addresses the SiPM geometric efficiency trade-off that limits LiDAR dynamic range. Standards bodies including ISO are actively developing LiDAR performance and safety standards that will influence SPAD specification requirements for automotive qualification.
Biophotonics and medical imaging
SPAD arrays provide the timing precision and single-photon sensitivity required for fluorescence lifetime imaging (FLIM), FRET, Raman spectroscopy, and positron emission tomography (PET). The EPFL AQUA group’s 2019 review covers SPAD-based endoscopic FLIM, super-resolution microscopy, near-infrared optical tomography (NIROT), and PET implementations with pixel-level time-stamping. FBK’s NUV-HD SiPM achieves 75–100 ps coincidence resolving time for PET scintillator readout, optimised for LYSO(Ce) crystal coupling. Columbia University’s 72×60 angle-sensitive SPAD array integrates diffraction gratings with SPAD pixels for lens-free 3D fluorescence lifetime mapping at micrometer scale.
Quantum communications and quantum photonics
SPADs are the room-temperature alternative to superconducting nanowire single-photon detectors (SNSPDs) for quantum key distribution, quantum computing readout, and entanglement experiments. IFN-CNR/Politecnico di Milano’s 2020 benchmarking study identifies SPAD advantages in room-temperature operation and scalability versus SNSPDs. The University of Geneva’s free-running InGaAs/InP SPAD (2007) achieved 10% detection efficiency at less than 2 kHz noise — a foundational result for fiber-optic QKD. National University of Singapore demonstrated radiation tolerance of Si APDs for satellite-based quantum communication at 400 km orbit, relevant to space-based QKD networks tracked by ESA and other space agencies.
Space astronomy and high-energy physics
University of Hawaii’s 2022 work on a 1-megapixel NIR APD array demonstrates HgCdTe linear-mode APD operation at 50 K achieving approximately 3 electrons per pixel per kilosecond dark current for exoplanet spectroscopy — an ultra-low background requirement that no silicon SPAD currently meets. In particle physics, University of Geneva’s 2022 Picosecond Avalanche Detector uses a multi-junction silicon pixel in 130 nm SiGe BiCMOS for charged-particle tracking with picosecond timestamps, while University of Barcelona’s 2010 comparison of HV 0.35 μm vs. 0.13 μm CMOS quantified the low DCR versus speed trade-off for tracking detectors in particle colliders.
SPAD applications span automotive LiDAR, biophotonics and medical imaging (FLIM, PET), quantum key distribution, free-space optical communications, high-energy physics particle detection, and space astronomy. Each application domain requires distinct trade-offs among photon detection efficiency, dark count rate, timing jitter, and fill factor — meaning a single SPAD architecture cannot optimally serve all verticals.
Identify white-space opportunities in SPAD patent claims across LiDAR, quantum, and imaging verticals.
Analyse with PatSnap Eureka →Five emerging directions in SPAD R&D (2022–2025)
Based on the most recent filings and publications in this dataset, five forward-looking directions are identifiable — each representing a distinct technical bet on how SPAD performance will be extended over the next three to five years.
1. Sub-4 μm pixel pitch SPAD arrays. Sony Semiconductor Solutions’ 3.06 μm SPAD pixel (2023) with embedded metal power grids and two-step deep trench isolation demonstrates that pixel pitch is approaching DRAM-class scaling. This trajectory points toward megapixel SPAD sensors competitive with conventional image sensors for consumer and automotive applications.
2. Advanced CMOS node integration (28 nm FD-SOI and beyond). STMicroelectronics’ 28 nm FD-SOI active quenching and reset circuit (2021) and subsequent pixel-level patents (2024–2025) signal that advanced node integration — enabling sub-40 ps avalanche detection and significant afterpulsing reduction — is becoming commercially deployable.
3. Stacked/bonded SPAD-logic substrate architectures. Adaps Photonics’ cluster of four US and WO patents (2021–2023) all describe sensor substrates bonded to logic substrates, a 3D integration approach that decouples optical optimisation of the SPAD from transistor scaling of the readout — mirroring the back-side illumination stacking transition in conventional CMOS image sensors.
4. Metasurface and photon-trapping nanostructure enhancement. China Jiliang University’s metasurface for SPAD (2020) and UC Davis’s photon-trapping nanostructure approach (2022) decouple photon absorption enhancement from device structure, enabling PDE improvements without degrading DCR or jitter — a compelling route for NIR-extended silicon SPADs.
5. Sb-based and Ge/GeSn heterogeneous APDs/SPADs for SWIR. University of Sheffield’s Sb-based low-noise APD review (2023) and Guangdong Greater Bay Area Institute’s Ge/GeSn and InGaAs SWIR APD review (2023) both signal an intensifying push to extend single-photon sensitivity into the 1.5–2.5 μm SWIR band, driven by LiDAR eye safety requirements and atmospheric transmission windows.
Strategic implications for IP and R&D teams
CMOS node migration is the primary competitive battleground: assignees controlling SPAD-compatible IP at the 28 nm FD-SOI and advanced nodes are positioned to dominate cost-sensitive high-volume markets such as automotive LiDAR and consumer time-of-flight. R&D teams should evaluate whether their device architectures are compatible with sub-65 nm processes before committing to custom process flows.
3D stacking will bifurcate the market. The bonded sensor-logic architecture demonstrated by Adaps Photonics and Sony decouples optical performance from digital scaling. IP strategists should monitor whether this approach creates a durable moat or whether foundry-standard stacking commoditises the integration advantage within three to five years — analogous to what happened with BSI CMOS image sensors.
“III-V and Ge-on-Si SPADs face a commercialisation window before silicon catches up: Ge-on-Si planar SPADs and InGaAs/InP devices remain the only viable single-photon options for telecom-wavelength quantum communications — but Sb-based and GeSn material systems emerging in 2022–2023 suggest the competitive landscape will fragment further.”
Application-specific optimisation is essential. PET scintillator readout (FBK NUV-HD SiPM with 75–100 ps CRT), quantum photonics (low DCR, low afterpulsing), and LiDAR (high fill factor, uniform breakdown) each demand distinct device parameter trade-offs. Portfolio strategies that attempt to serve all domains with a single SPAD architecture risk being out-performed by purpose-built competitors in each vertical. Research published through Nature and affiliated photonics journals consistently confirms that no single device architecture simultaneously optimises all five key SPAD performance metrics.
Among active patent assignees in this dataset, STMicroelectronics holds at least three active patents spanning CMOS SPAD device structures (2019–2025) and is the most prolific commercial SPAD patent assignee. Adaps Photonics holds four active patents concentrated on a single bonded-substrate platform (2021–2023). PixArt Imaging has filed three active or pending image sensor patents with SPAD-based pixel circuits in the 2023–2025 window, signalling aggressive recent commercialization in image sensing. The geographic concentration of active filings in the US, EP, and FR jurisdictions reflects both the location of leading foundries and the primary automotive and consumer electronics markets.