Why Sub-1ns Switching Triggers Parasitic Ringing in GaN and SiC Devices
The ringing problem in wide-bandgap power devices is not a design flaw — it is a direct consequence of physics. GaN HEMTs and SiC MOSFETs are capable of switching transitions orders of magnitude faster than silicon devices, owing to their higher critical electric field, wider bandgap, and lower intrinsic carrier concentration. As reviewed by the University of Southern Denmark (2022), these properties enable fast switching with lower power losses at higher switching frequency, enabling higher power density converters. But the same steep dV/dt and dI/dt ramps that make these transitions fast couple directly into the parasitic reactive elements of the surrounding circuit.
The primary mechanism is resonance between the parasitic inductance of the commutation loop and the output and junction capacitances of the switching devices. As explained in the Hanyang University paper on three-dimensional lattice structures (2023), fast switching induces voltage across parasitic inductances in the circuit, causing significant overshoot in the drain-source voltage and ringing of the drain current due to resonance with parasitic capacitances. The characteristic ringing frequency scales as 1/(2π√(LC)). When loop inductance L is in the range of 1–5 nH — typical of a well-designed PCB power loop — and device output capacitance C is in the range of 10–100 pF, the resulting ringing frequencies reach hundreds of MHz to several GHz, directly overlapping wireless communications bands and creating immediate EMI compliance challenges.
At sub-1ns switching transition times in GaN and SiC power devices, commutation loop inductances in the 1–5 nH range resonate with device output capacitances of 10–100 pF to produce ringing frequencies of hundreds of MHz to several GHz, as documented by Hanyang University (2023).
The problem is further compounded in half-bridge configurations by common-source inductance — the inductance shared between the gate loop and the power loop. Research from Daejin University (2021) documents how this shared inductance generates an undesired negative spike at the gate-source voltage during high-speed switching, and that ringing voltage occurs due to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs carry a lower gate voltage rating than conventional silicon devices, these negative gate voltage spikes directly threaten gate oxide reliability. This creates a hard reliability constraint that limits how aggressively switching speed can be increased without additional protective circuitry.
In half-bridge WBG converter configurations, the inductance shared between the gate drive loop and the power commutation loop creates a direct feedback mechanism. During fast switching, the dI/dt in the power loop induces a voltage across this shared inductance that appears as a negative spike at the gate-source terminal — threatening the gate oxide of SiC MOSFETs whose gate voltage ratings are lower than those of silicon IGBTs.
The Zhejiang University systematic review (2021) categorises oscillation mechanisms in discrete WBG packages, noting that switching oscillations are severe challenges associated with the discrete package format. The discrete package — ubiquitous in R&D and lower-volume production settings — is inherently more susceptible to ringing than custom power modules because bond wire and lead frame geometries introduce additional parasitic inductances that cannot be minimised to the same degree as a purpose-designed module. According to IEEE standards for power electronics, parasitic management is increasingly recognised as a first-order design constraint in high-frequency WBG converter development.
Gate Driver Strategies: The Most Patented Lever for Ringing Control
Gate driver design is the most widely patented lever for controlling the dV/dt and dI/dt profiles during WBG switching transitions, and the literature reflects intense innovation in this area. The fundamental tradeoff is direct: a slower gate drive reduces peak dV/dt and dI/dt, suppressing ringing amplitude, but increases switching energy losses. For sub-1ns target switching times, this tradeoff becomes extremely tight, since the gate resistance required to damp ringing to acceptable levels will typically extend the transition time well beyond 1 ns.
“In the case of a wide bandgap semiconductor, the reverse recovery is fast and thus a recovery current is not generated; however, the equivalent capacitance of the semiconductor induces oscillation.” — Mitsubishi Electric Corporation patent (EP, active, 2014)
Mitsubishi Electric’s approach addresses this asymmetrically. Its ON-speed reducing unit reduces the rate of change of the drive signal during turn-on to suppress recovery-related transients, while the OFF-speed improving unit draws charge from the switching element at high speed during turn-off. This asymmetric insight — that the absence of reverse recovery in WBG devices shifts the dominant ringing mechanism entirely to capacitive resonance — explains why silicon-era gate driver designs are insufficient for GaN and SiC applications. The same asymmetric logic is reinforced in patents by Yamada, Michio (US, active, 2017), which explicitly notes that raising the gate voltage quickly to increase switching speed improves switching loss but increases noise, establishing the direct tradeoff that all subsequent innovations attempt to resolve.
Ford Global Technologies LLC has developed an approach that operates at the circuit topology level rather than raw gate drive speed. Its drive circuit creates a period of operational overlap for the first and second switches by setting the gate voltage of the first switch to an intermediate value above the threshold voltage during the turn-on and turn-off operations of the second switch. By keeping the complementary device in a partially-on state during commutation of the active switch, the effective impedance of the commutation loop is modified and the Q-factor of the parasitic LC resonance is reduced. This approach is notable because it does not require slowing the gate drive ramp rate — it modifies the boundary conditions of the resonant circuit instead. Ford holds at least six active or recently inactive US and GB patents in this family filed between 2018 and 2021, indicating sustained strategic investment in this specific technique.
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Explore Patent Data in PatSnap Eureka →For parallel-connected WBG devices, Murata Manufacturing’s patent (US, 2021) proposes a fundamentally different approach: setting unbalanced driving impedances for the parallel power components so that only one component controls each switching transition. This prevents the inter-device oscillation that occurs when multiple parallel switches switch simultaneously and their gate and power loops interact — a distinct ringing mechanism from single-device commutation ringing. According to WIPO patent data, multi-device parallel WBG configurations represent a growing filing category as designers push power density beyond what a single device can deliver.
Ford Global Technologies LLC holds at least six active patents filed between 2018 and 2021 on an intermediate gate voltage overlap technique that suppresses parasitic ringing in wide-bandgap semiconductor devices by reducing the Q-factor of the parasitic LC resonance, without requiring a reduction in gate drive ramp rate.
Physical Limits: Packaging, PCB Layout, and Monolithic Integration
Beyond gate driver electronics, the physical structure of the power circuit is an independent and ultimately more fundamental constraint on achievable ringing. Fraunhofer IISB (2022) states this directly: there is a physical limit for reducing the parasitic inductance of the commutation cell, and this is one of the reasons why the full potential of wide-bandgap devices cannot be entirely utilised. No gate driver design, however sophisticated, can eliminate ringing caused by a commutation loop inductance that cannot be physically reduced further.
IMEC (2019) reported that a two-stage gate driver and power GaN HEMT fabricated on the same GaN-on-SOI chip reduced switching time by 86% at turn-off and by 45% at turn-on compared to a conventional discrete gate driver circuit, under 100 V drain-source voltage and 10 A drain current. The mechanism is explicit: monolithic integration improves switching performance owing to minimised parasitic inductance between gate driver output and device gate terminal.
Oak Ridge National Laboratory (2018) provides a detailed engineering case study for discrete implementations. Designing for a 3L-ANPC converter based on 650 V GaN HEMTs, the team developed an ultralow inductance power cell using a four-layer PCB specifically aimed at maximising switching performance. The commutation loops — which mainly contribute to voltage overshoots and increase of switching losses — were explicitly targeted in the layout design, with finite-element analysis used to extract parasitic inductance and resistance of the final design. This represents the state of the art in discrete PCB-based WBG power circuits, as recognised in PatSnap’s power electronics research coverage.
Hanyang University’s 3D lattice structure paper (2023) proposes a more radical PCB architecture: a three-dimensional lattice that achieves parasitic inductance reduction through horizontal and vertical magnetic flux cancellations within the PCB itself. The relationship between magnetic flux cancellation and parasitic inductance is analysed explicitly, demonstrating that conventional 2D planar PCB layouts leave substantial inductance reduction potential unrealised.
A complementary approach from Politecnico di Torino (2021) proposes deliberately exploiting the source inductance of the power transistor — an element normally treated purely as a parasitic — by optimising it in combination with an external inductance to damp oscillations caused by the turn-on transition. This technique achieved a 20 dB attenuation of conducted emission at the oscillation frequency, representing a design philosophy shift: rather than minimising all parasitic inductance universally, selectively tuning specific parasitic elements to achieve damping. The OECD‘s analysis of power electronics innovation trends identifies EMI compliance as one of the primary commercial drivers pushing this kind of nuanced parasitic management strategy.
IMEC (2019) demonstrated that monolithic co-integration of a two-stage gate driver and power GaN HEMT on the same GaN-on-SOI chip reduced turn-off switching time by 86% and turn-on switching time by 45% compared to a discrete gate driver circuit operating at 100 V drain-source voltage and 10 A drain current, by eliminating bondwire and PCB trace inductances between the gate driver and device gate terminal.
The packaging challenge for WBG modules is addressed in the 2018 review of high-performance packaging technology for wide-bandgap semiconductor modules, which notes that first-generation WBG devices used conventional packaging technologies designed for silicon, and that the full benefits of WBG switching speed cannot be realised without purpose-designed low-inductance module packaging. The lumped parameter modelling approach from Daejin University (2021) further provides an analytical method for quantifying how power loop parasitic inductances affect reliability at high dV/dt and dI/dt levels, enabling iterative PCB and module layout optimisation without requiring hardware prototyping at each design iteration. This analytical capability is increasingly referenced in PatSnap’s innovation intelligence resources as a key enabler for accelerating WBG product development cycles.
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Search Patent Intelligence in PatSnap Eureka →Zero Overvoltage Switching and Emerging Paradigms for Sub-1ns Operation
Zero Overvoltage Switching (ZOS), analysed by Fraunhofer IISB (2022), represents the most conceptually radical departure from conventional ringing-suppression approaches in the dataset. Rather than treating parasitic oscillating elements as problems to be suppressed, ZOS deliberately triggers the inherent parasitic oscillating elements of a commutation cell to perform an ideal current commutation. The theoretical result is unlimited switching speed with no switching losses and no voltage overshoots — a complete inversion of the conventional design paradigm.
“There is a physical limit for reducing the parasitic inductance of the commutation cell, and this is one of the reasons why the full potential of wide-bandgap devices cannot be entirely utilised.” — Fraunhofer IISB, Analysis of the Zero Overvoltage Switching Phenomenon, 2022
The Fraunhofer analysis investigates ZOS in real-world applications by adapting the model of an ideal commutation cell. While it acknowledges the gap between the theoretical ideal and practical implementation, it establishes ZOS as a physically grounded phenomenon that can theoretically circumvent the parasitic inductance limit that constrains all other approaches. Practical implementation in real-world power converters remains an open research challenge.
Predictive modelling has matured sufficiently to guide snubber design without iterative hardware prototyping. Grenoble INP (2021) presents methods for PCB layout parameter extraction and model reduction to obtain a lumped inductance of the input filter PCB for the analytical prediction of transistor turn-off ringing frequency and overvoltage — validated against measurements and used directly for sizing optimal snubber capacitance. The University of Lille (2021) similarly co-simulates device compact models with parasitic inductance physical models, enabling switching waveform prediction at the design stage. Standards bodies including IEC are actively developing measurement standards for WBG switching waveform characterisation that will rely on these modelling methodologies.
Zero Overvoltage Switching (ZOS), as analysed by Fraunhofer IISB (2022), deliberately triggers the inherent parasitic oscillating elements of a WBG commutation cell to perform an ideal current commutation, with the theoretical result of unlimited switching speed and zero voltage overshoot — but practical implementation in real-world power converters remains an open research challenge as of 2022.
For very high switching speeds with multiple series-connected devices, Fermilab (2018) demonstrated 600 V pulse generation with 2 ns rise/fall time using four series-connected enhancement-mode GaN transistors driven by a microwave photonics synchronisation system. The photonic distribution system achieves precise synchronisation between transistors, preventing the inter-device timing skew that would otherwise generate ringing between individual switching events. While specific to pulsed accelerator applications, this illustrates the synchronisation precision required when pushing WBG switching into the sub-2 ns regime.
Patent Landscape and Key Innovation Clusters in WBG Ringing Suppression
The patent and literature corpus reviewed spans approximately 40 sources, and the dominant assignees in the patent space reveal clear strategic priorities. Ford Global Technologies LLC is the most prolific patent assignee in this specific domain, holding a family of at least six patents filed 2017–2021 across US and GB jurisdictions, all centred on the intermediate gate voltage overlap technique. The consistent continuation-in-part filing strategy indicates active prosecution and broadening of this IP position, likely motivated by Ford’s EV traction inverter programmes. Mitsubishi Electric Corporation holds patents in multiple jurisdictions on the asymmetric gate drive speed approach, while Toyota Motor Corporation holds multiple active and inactive patents in a Power Conversion Device family focusing on hybrid WBG/Si parallel switch configurations.
The overall innovation trend documented across the dataset is a shift from single-lever approaches — gate resistor tuning — toward multi-layer co-optimisation. Gate driver waveform shaping, PCB and module parasitic minimisation, and topology-level boundary condition control are being combined simultaneously, reflecting the recognition that no single technique is sufficient to reach sub-1 ns switching with acceptable ringing at practical power levels. Academic and national laboratory contributions from Fraunhofer IISB, Oak Ridge National Laboratory, and IMEC are establishing the theoretical and experimental foundations that patent filers are translating into commercial IP.