Why Sub-1ns Switching in GaN and SiC Devices Triggers Parasitic Ringing
At sub-1ns transition times, even commutation loop inductances in the single-nanohenry range — unavoidable in any physical PCB layout — become dominant impedances that resonate with device output and junction capacitances, producing ringing frequencies from hundreds of MHz to several GHz. This is not a design immaturity problem; it is a direct consequence of the same material properties that make wide-bandgap semiconductors desirable.
GaN HEMTs and SiC MOSFETs possess higher critical electric fields, wider bandgaps, and lower intrinsic carrier concentrations than silicon — properties that, as reviewed by the University of Southern Denmark (2022), enable fast switching with lower power losses at higher switching frequencies, enabling higher power density converters. The challenge is that the extremely steep dV/dt and dI/dt ramps couple directly into the parasitic reactive elements of the surrounding circuit.
The primary mechanism is resonance between commutation loop inductance and device capacitances. As established by Hanyang University (2023), the fast switching speed of WBG power semiconductors induces voltage across parasitic inductances in the circuit, causing significant overshoot in the drain-source voltage and ringing of the drain current due to resonance with parasitic capacitances. The characteristic ringing frequency scales as 1/(2π√(LC)): with L in the range of 1–5 nH (typical of a well-designed PCB power loop) and C in the range of 10–100 pF (device output capacitance), ringing frequencies can reach hundreds of MHz to several GHz — directly overlapping wireless communications bands and creating immediate EMI compliance risks.
In wide-bandgap power converter designs, commutation loop inductances of 1–5 nH combined with device output capacitances of 10–100 pF produce parasitic ringing at frequencies from hundreds of MHz to several GHz when switching transitions occur in the sub-nanosecond range.
The problem is further compounded in half-bridge configurations by common-source inductance — the inductance shared between the gate loop and the power loop. Research from Daejin University (2021) documents that this shared inductance creates a feedback mechanism generating an undesired negative spike at the gate-source voltage during high-speed switching, and ringing voltage occurs due to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs carry lower gate voltage ratings than conventional silicon devices, these negative spikes directly threaten gate oxide reliability — a hard constraint on how aggressively switching speed can be increased without additional protective circuitry.
In silicon IGBTs, the dominant transient at turn-on is reverse recovery current from the freewheeling diode. In WBG devices, reverse recovery is negligible — the dominant ringing mechanism shifts entirely to capacitive resonance during the fast turn-off transient. As Mitsubishi Electric’s EP patent family explicitly states: in the case of a wide bandgap semiconductor, the reverse recovery is fast and thus a recovery current is not generated; however, the equivalent capacitance of the semiconductor induces oscillation. This distinction renders silicon-era gate driver designs structurally insufficient for WBG applications.
The discrete package format — ubiquitous in R&D and lower-volume production — is inherently more susceptible to ringing than custom power modules. A systematic review by Zhejiang University (2021) categorises switching oscillations as severe challenges associated with the discrete package format, noting that bond wire and lead frame geometries introduce additional parasitic inductances that cannot be minimised to the same degree as a purpose-designed module. According to IEEE published research in this domain, the gap between theoretical WBG switching capability and what is achievable in discrete hardware is substantial and well-documented.
Gate Driver Strategies: The Principal Mitigation Tool and Its Limits
The gate driver is the most widely patented lever for controlling dV/dt and dI/dt profiles during WBG switching transitions — but the fundamental tradeoff is unforgiving: slowing the gate drive ramp rate suppresses ringing amplitude while directly increasing switching energy losses. For sub-1ns target switching times, the gate resistance required to damp ringing to acceptable levels will typically extend the transition time well beyond 1 ns.
The patent landscape reveals two dominant strategic responses to this tradeoff. The first — represented by Mitsubishi Electric’s EP patent family (2014) and Yamada, Michio’s US patent (2017) — is the asymmetric gate drive profile: slow turn-on, fast turn-off. The Mitsubishi approach employs an ON-speed reducing unit that reduces the rate of change of the drive signal during turn-on to suppress recovery-related transients, while an OFF-speed improving unit draws charge from the switching element at high speed during turn-off. The rationale is grounded in the physics of WBG devices: the absence of reverse recovery current at turn-on means that the dominant ringing mechanism is capacitive resonance during turn-off, so fast turn-off is permissible with controlled turn-on. The Yamada patent reinforces this consensus, explicitly noting that raising the gate voltage quickly to increase switching speed improves switching loss but increases noise.
“In the case of a wide bandgap semiconductor, the reverse recovery is fast and thus a recovery current is not generated; however, the equivalent capacitance of the semiconductor induces oscillation.” — Mitsubishi Electric EP patent family
The second strategy — Ford Global Technologies’ intermediate gate voltage overlap technique, documented across at least six active patents filed 2017–2021 — operates at the circuit topology level rather than the raw gate drive speed level. Ford’s drive circuit creates a period of operational overlap for the first and second switches by setting the gate voltage of the first switch to an intermediate value above the threshold voltage during the turn-on and turn-off operations of the second switch. By keeping the complementary device partially on during commutation, the effective impedance of the commutation loop is modified and the Q-factor of the parasitic LC resonance is reduced — without requiring any reduction in the gate drive ramp rate. This is a structurally different solution: it changes the boundary conditions of the resonant circuit rather than damping it.
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Analyse Patents with PatSnap Eureka →For parallel-connected WBG devices, Murata Manufacturing’s US patent (2021) addresses a distinct ringing mechanism: inter-device oscillation that occurs when multiple parallel switches switch simultaneously and their gate and power loops interact. Murata’s solution sets unbalanced driving impedances for the parallel power components so that only one component controls each switching transition, preventing the simultaneous commutation that excites inter-device ringing. This is a different problem from single-device commutation ringing and requires a different solution — a distinction that the patent literature makes explicit.
Ford Global Technologies LLC holds at least six active patents filed between 2017 and 2021 on the intermediate gate voltage overlap technique for minimising ringing in wide-bandgap semiconductor devices, making it the most extensively patented single ringing mitigation technique in this domain.
Packaging, PCB Layout, and Monolithic Integration: The Physical Constraint Layer
Beyond gate driver electronics, the physical structure of the power circuit imposes an independent and ultimately more fundamental constraint on achievable ringing. Fraunhofer IISB (2022) states directly: there is a physical limit for reducing the parasitic inductance of the commutation cell, and this is one of the reasons why the full potential of wide-bandgap devices cannot be entirely utilised. No gate driver design, however sophisticated, can eliminate ringing caused by a commutation loop inductance that cannot be physically reduced further.
Oak Ridge National Laboratory (2018) provides a detailed engineering case study for a 3L-ANPC converter based on 650 V GaN HEMTs, developing an ultralow inductance power cell using a four-layer PCB specifically aimed at maximising switching performance. The commutation loops — which mainly contribute to voltage overshoots and increase of switching losses — were explicitly targeted in the layout design, with finite-element analysis used to extract parasitic inductance and resistance of the final design. According to the U.S. Department of Energy, Oak Ridge National Laboratory is a primary federally-funded research centre for wide-bandgap power electronics.
Hanyang University (2023) proposes a more radical PCB architecture: a three-dimensional lattice structure that achieves parasitic inductance reduction through horizontal and vertical magnetic flux cancellations within the PCB itself. The relationship between magnetic flux cancellation and parasitic inductance is analysed explicitly, demonstrating that conventional 2D planar PCB layouts leave substantial inductance reduction potential on the table.
IMEC (2019) reported that a two-stage gate driver and power GaN HEMT fabricated on the same GaN-on-SOI chip reduced switching time by 86% at turn-off and by 45% at turn-on compared to a conventional discrete gate driver circuit, under 100 V drain-source voltage and 10 A drain current. The mechanism is the elimination of bondwire and PCB trace inductances between the gate driver output and the device gate terminal — typically 1–10 nH in discrete implementations — reducing effective gate loop inductance to the sub-100 pH range achievable in integrated circuit layouts.
A complementary approach from Politecnico di Torino (2021) represents a design philosophy shift: rather than minimising all parasitic inductance universally, it proposes deliberately exploiting the source inductance of the power transistor — normally treated purely as a parasitic — by optimising it in combination with an external inductance to damp oscillations caused by the turn-on transition. The result was a 20 dB attenuation of conducted emission at the oscillation frequency. This technique of selective parasitic tuning rather than universal minimisation is conceptually aligned with the Zero Overvoltage Switching paradigm discussed in the next section.
IMEC (2019) demonstrated that monolithic co-integration of a two-stage gate driver and p-GaN power HEMT on the same GaN-on-SOI chip reduced turn-off switching time by 86% and turn-on switching time by 45% compared to a conventional discrete gate driver circuit operating at 100 V drain-source voltage and 10 A drain current, by reducing effective gate loop inductance from the 1–10 nH range of discrete implementations to the sub-100 pH range achievable in integrated circuit layouts.
The packaging challenge for WBG modules is addressed in a 2018 review which notes that first-generation WBG devices used conventional packaging technologies designed for silicon, and that the full benefits of WBG switching speed cannot be realised without purpose-designed low-inductance module packaging. The Daejin University (2021) lumped parameter modelling study provides an analytical method for quantifying how power loop parasitic inductances affect reliability at high dV/dt and dI/dt levels, enabling iterative PCB and module layout optimisation without requiring repeated hardware prototyping. Standards bodies including IEC are actively developing test and characterisation standards for WBG power module packaging to address this gap.
Map the full IP landscape for WBG power module packaging and PCB layout innovations in PatSnap Eureka.
Explore Patent Data in PatSnap Eureka →Zero Overvoltage Switching and the Emerging Paradigm of Exploiting Parasitics
Zero Overvoltage Switching (ZOS), analysed by Fraunhofer IISB (2022), inverts the conventional design paradigm entirely: rather than suppressing parasitic oscillating elements, ZOS deliberately triggers them to perform an ideal current commutation. The theoretical result is unlimited switching speed with no switching losses and no voltage overshoots — a complete inversion of every other approach in this analysis.
The Fraunhofer analysis investigates this phenomenon in real-world applications by adapting the model of an ideal commutation cell. While it acknowledges the gap between theoretical ideal and practical implementation, it establishes ZOS as a physically grounded phenomenon that can theoretically circumvent the parasitic inductance limit that constrains all other approaches. Critically, Fraunhofer IISB also acknowledges that there is a physical limit for reducing the parasitic inductance of the commutation cell — meaning ZOS is not merely a theoretical curiosity but a response to a real engineering ceiling that conventional approaches cannot breach.
Zero Overvoltage Switching (ZOS), as analysed by Fraunhofer IISB in 2022, deliberately triggers the inherent parasitic oscillating elements of a WBG power converter commutation cell to perform an ideal current commutation, theoretically achieving unlimited switching speed with no switching losses and no voltage overshoots — the opposite strategy to all conventional ringing suppression approaches.
Complementary modelling work from Grenoble INP (2021) demonstrates that predictive circuit modelling is now sufficiently mature to guide snubber design without iterative hardware prototyping. Their wideband model of a DC-DC buck converter with GaN transistors provides methods for PCB layout parameter extraction and model reduction to obtain a lumped inductance of the input filter PCB for the analytical prediction of transistor turn-off ringing frequency and overvoltage, validated against measurements. Similarly, the University of Lille (2021) co-simulates GaN HEMT compact models with parasitic inductance physical models, enabling switching waveform prediction at the design stage — a capability that is essential for ZOS optimisation, where the parasitic elements must be precisely characterised rather than minimised.
At the extreme end of switching speed, Fermilab (2018) demonstrated 600 V pulse generation with 2 ns rise/fall time using four series-connected enhancement-mode GaN transistors driven by a microwave photonics synchronisation system. The photonic distribution system achieves precise synchronisation between transistors, preventing the inter-device timing skew that would otherwise generate ringing between individual switching events. While specific to pulsed accelerator applications, this illustrates the synchronisation precision required when pushing WBG switching into the sub-2 ns regime — a requirement that will equally apply to any future commercial sub-1 ns power converter. Research institutions including NIST are engaged in developing measurement standards for sub-nanosecond power electronics characterisation.
“There is a physical limit for reducing the parasitic inductance of the commutation cell — this is one of the reasons why the full potential of wide-bandgap devices cannot be entirely utilised.” — Fraunhofer IISB, 2022
The Politecnico di Torino (2021) source inductance optimisation work — achieving 20 dB conducted emission attenuation by tuning rather than minimising a specific parasitic — is philosophically aligned with ZOS. Both approaches recognise that at sub-1 ns switching speeds, parasitic elements are not merely nuisances to be eliminated but resonant resources that can be engineered to produce desired outcomes. This represents the emerging frontier of WBG power electronics design: from parasitic minimisation to parasitic engineering.
Key Patent Holders, Research Institutions, and the Multi-Layer Innovation Trend
The innovation landscape for sub-1ns WBG switching ringing mitigation is structured around a small number of dominant assignees and research institutions, each pursuing distinct technical approaches with clear strategic motivations.
Ford Global Technologies LLC is the most prolific patent assignee in this specific domain, with a family of at least six patents (filed 2017–2021, across US and GB jurisdictions) all centred on the intermediate gate voltage overlap technique. The consistent continuation-in-part filing strategy indicates active prosecution and broadening of this IP position, likely motivated by Ford’s EV traction inverter programmes.
Mitsubishi Electric Corporation holds patents in multiple jurisdictions (EP active, IN inactive) on the asymmetric gate drive speed approach for WBG switching elements, emphasising fast turn-off and controlled turn-on slew rate specifically for the WBG context.
Toyota Motor Corporation holds multiple active and inactive patents (US and EP) in a Power Conversion Device family, focusing on hybrid WBG/Si parallel switch configurations. While these address switching loss distribution rather than ringing directly, they represent a systems-level approach to managing the speed–loss tradeoff.
Murata Manufacturing Co., Ltd. contributes the unbalanced impedance approach to parallel-switch oscillation suppression — addressing a distinct ringing mechanism from single-device commutation ringing.
Fraunhofer IISB is the key academic innovator behind the ZOS concept, representing the most theoretically radical departure from conventional ringing-suppression approaches. Oak Ridge National Laboratory and IMEC represent the leading publicly-funded research centres in low-inductance power cell design and monolithic GaN integration respectively, with findings from the University of Southern Denmark, Daejin University, Zhejiang University, Hanyang University, Politecnico di Torino, Grenoble INP, and the University of Lille rounding out the academic corpus. The World Intellectual Property Organization (WIPO) patent database reflects the global nature of this IP race, with filings spanning US, EP, GB, IN, and JP jurisdictions.
The overall innovation trend is a shift from single-lever approaches — gate resistor tuning — toward multi-layer co-optimisation: gate driver waveform shaping, PCB and module parasitic minimisation, and topology-level boundary condition control are being combined simultaneously. This reflects the recognition across both patent assignees and research institutions that no single technique is sufficient to reach sub-1 ns switching with acceptable ringing at practical power levels. The emergence of ZOS and selective parasitic engineering as active research directions suggests that the next generation of solutions may abandon the suppression paradigm altogether.