How wafer-level fan-out packaging works: structure and RDL mechanics

Wafer-level fan-out (WLFO) packaging completes the packaging process at the wafer level—either without separating dies from the wafer, or by rearranging individual dies into a reconstituted wafer form—before final singulation. A redistribution layer (RDL) formed on a passivation layer electrically connects each chip’s I/O pads to external contacts, fanning signals out beyond the die’s physical footprint without a conventional organic or ceramic substrate. That substrate-free architecture is the defining departure from every legacy approach.

The RDL is the technological heart of WLFO. By routing signals laterally through patterned metal layers deposited directly on the chip surface and encapsulant, the package can present a much larger ball pitch to the PCB while maintaining extremely dense die-level interconnect—without the signal path ever traversing a laminate substrate. This is why WLFO can achieve interconnect pitches well below 2 µm, compared to the 100–150 µm solder bump pitch typical of flip-chip ball grid array (FC-BGA) packages.

Warpage: the primary yield risk in large-format WLFO

The most significant manufacturing challenge in WLFO is package warpage. When a reconstituted wafer contains chips surrounded by molding compound, the mismatch in thermal expansion coefficients and Young’s moduli between the molding compound, embedded dies, and any reinforcement layers causes the wafer to bow during thermal cycling—directly reducing yield. For large-format packages used in AI accelerators, this is not a minor process nuisance; it is the primary limiter on production economics.

Thermal management embedded in the fan-out stack

Modern AI processors carry thermal design power (TDP) values in the 300–700 W range, making thermal management a co-equal design constraint alongside signal integrity. WLFO addresses this by integrating heat spreaders directly into the package stack. In the architecture described by the Guangdong Academy of Sciences Semiconductor Institute (2021), the chip’s back face bonds via adhesive to the heat spreader’s die-attach region, encapsulant fills the gaps between the heat spreader and chip protection material, and package wiring grows directly on the chip’s front face, the encapsulant surface, and the heat spreader’s protruding structures. The result is a fan-out package explicitly designed for “high power density chips” with improved operating power and reduced power consumption—properties that substrate-bound packaging cannot replicate without adding separate thermal interface layers and heat slugs that increase package height and thermal resistance.

Multi-die WLFO is enabled by arranging dies side-by-side within the reconstituted wafer and routing die-to-die signals through the RDL rather than through a package substrate or PCB. MediaTek’s 2016 EP patent demonstrates this configuration, with connection paths linking I/O pads on adjacent die sides—a foundational technique that directly enables chiplet-based AI processors where logic, memory, and I/O tiles must communicate at high bandwidth and low latency within a single package boundary.

3D die stacking and heterogeneous integration for AI workloads

Three-dimensional die stacking combines the substrate-free advantages of WLFO with vertical integration of compute and memory dies, addressing the memory bandwidth bottleneck that defines AI training and inference workloads. The stacking order is not architecturally neutral—it has direct thermal consequences that patent filers are now explicitly resolving.

Kepler Computing’s 2025 CN patent describes an IC package in which a first die containing DRAM is placed below a second die containing compute logic, coupled via micro-bumps in a wafer-to-wafer bonding configuration. The thermal engineering rationale is explicit: “placing the compute die below the DRAM die leads to thermal problems for the compute die, because any heat sink is closer to the DRAM and farther from the compute die.” By inverting the stack—memory below, compute above—and aligning TSV density directly with die-to-die I/O count, the architecture achieves area-array bandwidth rather than the perimeter-limited bandwidth of conventional flip-chip arrangements.

“Placing HBM on the sides of a compute die in a conventional flip-chip arrangement does not solve the bandwidth problem because bandwidth is constrained by peripheral I/O from each side of the HBM and compute die.” — Kepler Computing, 2025

Panasonic IP Management’s 2022 CN patent refines the multi-die stacking model further, stacking multiple memory dies and multiple compute dies on a system chip, with each die type maintaining its own independently optimized layout. An interposer can be incorporated optionally—enabling memory and compute dies to be redesigned independently without redesigning the entire system chip, thereby increasing configuration flexibility. When the interposer is omitted, cost reduces without sacrificing the core stacking architecture.

System-on-wafer: eliminating the PCB entirely

The logical frontier of WLFO philosophy is the system-on-wafer (SoW), in which multiple chips are mounted directly on semiconductor wafers, interconnected via wiring layers and power modules, with inter-wafer connectors linking SoWs together. A 2025 WO patent filing explicitly critiques the conventional PCB-integrated server format, noting it “imposes limitations on thermal efficiency, power efficiency, and bandwidth availability, and may result in a relatively large physical footprint.” By eliminating the PCB substrate entirely in favor of wafer-native interconnect at the system level, SoW architectures represent the maximum expression of the trends that began with single-chip WLFO packages in the 2010s.

Heterogeneous integration at the wafer scale also enables independent optimisation of each die type. Logic dies can be fabricated at the leading process node for maximum compute density, while memory dies use nodes optimised for density and cost, and I/O dies use nodes optimised for high-voltage tolerance—all integrated within a single WLFO or SoW boundary. According to WIPO patent trend data, heterogeneous integration filings have accelerated significantly across US, CN, EP, WO, and KR jurisdictions since 2020, reflecting the industry’s recognition that no single process node can simultaneously optimise all functions of a modern AI chip.

Where flip-chip BGA hits its ceiling in AI systems

Flip-chip BGA remains the dominant volume packaging technology for CPUs and discrete GPUs, and it retains cost advantages for single-die, high-volume designs with well-understood I/O requirements. However, the patent record is explicit about where FC-BGA’s architecture becomes structurally inadequate for AI-scale workloads.

The bandwidth ceiling of FC-BGA manifests at three levels. First, at the die level: neural network inference and training are memory-bandwidth-bound, and the C4 solder bump array that connects the die to the package substrate is a perimeter-limited interface. Placing HBM on the sides of a compute die in a conventional flip-chip arrangement constrains bandwidth to the number of peripheral I/Os on each die edge—an area that scales linearly with die perimeter rather than quadratically with die area. Second, at the package level: the organic or ceramic substrate that FC-BGA requires is itself a routing bottleneck, with trace widths and via densities that cannot match the sub-2 µm RDL achievable in WLFO. Third, at the system level: IBM’s 2015 CN patent on packaging for eight-socket, one-hop SMP topologies documents that “it is impossible to use packaging technology described in the prior art to achieve high bandwidth, eight-node, one-hop systems” using standard socket-based packaging with land grid array (LGA) connectors—requiring multi-plane vertical stacking as a workaround that effectively demonstrates the density ceiling of conventional substrate-based approaches.

For smaller AI inference chips—edge AI in wearables and audio applications, for instance—FC-BGA and even simpler wire-bonding approaches on PCB substrates remain viable. Shenzhen Jiutian Ruixin Technology’s 2023 patent demonstrates that system-in-package integration of AI, ASIC, and MEMS chips can be accomplished via wire bonding, suitable for edge deployments with constrained I/O and thermal requirements. The critical distinction is scale: as AI workload size grows and memory bandwidth requirements intensify, the architectural limitations of FC-BGA become mandatory constraints rather than engineering trade-offs. Standards bodies including JEDEC and the IEEE have both published specifications for HBM and advanced packaging interconnect that reflect this bandwidth-driven transition away from conventional solder-bump architectures.

Head-to-head: WLFO vs. flip-chip BGA across eight attributes

Across the eight attributes most relevant to AI chip packaging decisions, WLFO and FC-BGA present a clear trade-off profile: WLFO wins on interconnect density, bandwidth, thickness, and chiplet scalability; FC-BGA retains advantages in manufacturing maturity, warpage resistance, and unit cost for single-die designs.

The warpage disadvantage of WLFO is now being systematically addressed through composite structural engineering. JCET Advanced Packaging’s 2023 patent introduces a sheet-like structural layer with defined apertures housing each chip, with the aperture-to-solid ratio controlled within (0.5–2):1. Because the Young’s modulus of the plastic packaging layer is lower than that of the structural layer, the composite system achieves reduced package warpage and improved package strength—directly improving yield for large-format AI accelerator packages. The thermal disadvantage is addressed by Guangdong Academy of Sciences’ heat-spreader-embedded fan-out structure, which routes thermal energy through the package stack rather than relying on a separate lid or heat slug bonded above the substrate.

Key patent assignees and the innovation clusters shaping AI packaging

The patent dataset spanning US, CN, EP, WO, and KR jurisdictions reveals three distinct innovation clusters, each addressing a different layer of the WLFO and advanced AI packaging stack.

Packaging foundries and OSATs

JCET Advanced Packaging—China’s largest outsourced semiconductor assembly and test (OSAT) provider—is active in WLFO structural innovations specifically targeting warpage control, a critical production yield issue for large-format packages. STS Semiconductor & Telecommunications (Korea) holds foundational WLFO process patents covering RDL formation, passivation layering, and wafer-scale singulation, establishing the baseline manufacturing framework from which subsequent innovations depart. The Guangdong Academy of Sciences Semiconductor Institute is pursuing thermally enhanced fan-out structures with integrated heat spreaders for high-power-density applications—directly relevant to AI processors with TDP values in the 300–700 W range.

Fabless AI chip and system designers

Panasonic IP Management is patenting scalable AI chip architectures using die-stacking with optional interposers, enabling independent redesign of memory and compute dies. Kepler Computing is specifically addressing the compute-over-memory 3D die-stacking configuration for ultra-high bandwidth AI inference and training, with explicit thermal and bandwidth co-optimisation. Taichu (Wuxi) Electronic Technology is integrating network switching and routing logic directly onto AI chips to eliminate the PCIe external interconnect bottleneck—a recognition that the bandwidth problem extends beyond the package boundary to the system interconnect fabric.

Multi-die and chiplet system architects

MediaTek holds key patents on side-by-side multi-die wafer-level packages with die-to-die RDL interconnect, a foundational technique for chiplet-based AI processors. A 2025 WO filing extends the WLFO concept to full system-on-wafer architectures for AI server infrastructure, proposing inter-wafer connectors that link SoWs together to form compute clusters without PCB intermediaries. IBM’s documented architectural ceiling for conventional substrate-based packaging in multi-processor HPC topologies motivates the entire vertical stacking and wafer-scale integration trajectory now visible across 2021–2025 filings.

A clear convergence is visible across the 2021–2025 filings: thermal management, ultra-high-bandwidth memory integration, and wafer-scale interconnect are now treated as co-equal design constraints—none of which can be adequately addressed by conventional FC-BGA alone. The Semiconductor Industry Association has similarly identified advanced packaging as a critical technology pillar in its roadmap for sustaining semiconductor performance scaling beyond traditional transistor density improvements. This institutional recognition reinforces the patent-level evidence that WLFO and 3D stacking are no longer niche techniques—they are the primary engineering response to the bandwidth and thermal demands of AI compute at scale.