Patent Drafting Analysis of Applied Materials’ Secured Crypto Processor for Chiplet Security Using AI | US 2025/0079342 A1
Patent Drafting Analysis of Applied Materials' Secured Crypto Processor for Chiplet Security Using AI | US 2025/0079342 A1
A structural and strategic analysis of Applied Materials' AI-driven chiplet anomaly detection patent, examining claim architecture, drafting quality, §101 eligibility risks, critical gaps, and prosecution positioning across system, method, and CRM claim types.
Spec Words
7,200
Across 6 sections
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Total Claims
20
3 independent · 17 dependent
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Figure Sheets
7
System architecture, block diagrams, encryption datapath, flowchart
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Published by PatSnap Insights Team · · 12 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 54% of total words (~3,900 words), providing substantial embodiment support across hardware monitoring, reinforcement learning, and cryptographic operations. The claim set totals 20 claims — 3 independent claims covering system (Claim 1), method (Claim 11), and CRM (Claim 18) formats — with 17 dependents yielding a 5.67:1 dependent-to-independent ratio. Figure coverage spans 7 sheets addressing physical chiplet layout (FIG. 1), heterogeneous system architecture (FIG. 2–3), AI/cryptography hardware detail (FIG. 4–5), operational flowchart (FIG. 6), and a generalized computer system (FIG. 7).
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 7 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1 | Illustrates a chiplet-based system 100 showing an interposer 102 with multiple chiplets 104-1 through 104-6 mounted on it as separate dies.Search in Eureka ↗ | Key embodiment |
| FIG. 2 | Illustrates heterogeneous chiplet system 200 showing root-of-trust 202 boundary containing peripherals 206, multicore host CPU 208, AI processing subsystem 210, and cryptography subsystem 212 connected via interposer 204, with untrusted chiplets 214 outside the boundary.Search in Eureka ↗ | System architecture |
| FIG. 3 | Block diagram 300 detailing the AI/cryptography subsystem configuration showing trusted components 302, monitoring system 304, AI/ML processor 306, chiplet-to-chiplet security module 308 inside root-of-trust, and corresponding chiplet-to-chiplet security 310 in untrusted chiplets 214.Search in Eureka ↗ | Key embodiment |
| FIG. 4 | Block diagram 400 of AI/cryptography hardware implementation showing hardware monitors 402 (cache miss, memory access, power, temperature, sender IP), monitor block 404 with registers and programmable controller, AI accelerator 406 with master controller 408, SRAM 410, FMA units, RL block, DRAM 422, and configurable security IP 414 with key size 416, message length 418, and scalable chiplet parameters 420.Search in Eureka ↗ | Claim support |
| FIG. 5 | Illustrates encryption data path 500 implemented by cryptography block 414, showing key register, data register, substitution boxes (S-Boxes) implemented as scalable chiplets, permutation layer (P-Layer), and counter (CTR) for symmetric block cipher based on substitution-permutation network.Search in Eureka ↗ | Claim support |
| FIG. 6 | Flowchart 600 of method for identifying anomalies in untrusted chiplets, showing steps: monitor state of first chiplet (602), select action affecting second chiplet (604), cause action to be performed (606), and execute reinforcement learning algorithm to update actions (608).Search in Eureka ↗ | Flow diagram |
| FIG. 7 | Illustrates exemplary computer system 700 showing processing unit 704, processing acceleration unit 706, I/O subsystem 708, system memory 710, storage subsystem 718, and communications subsystem 724 with data feeds 726, event streams 728, and event updates 730.Search in Eureka ↗ | Other |
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Claims
Claim Architecture Analysis
The patent presents 3 independent claims: Claim 1 (system/apparatus), Claim 11 (method), and Claim 18 (CRM), providing tripartite enforcement coverage. The 17 dependent claims yield a 5.67:1 dependent-to-independent ratio, which is above the semiconductor/hardware norm of approximately 4–5:1, suggesting reasonable fallback layering. Notably, the dependent claims are unevenly distributed — Claims 2–10 depend from system Claim 1 (9 dependents), Claims 12–17 depend from method Claim 11 (6 dependents), and Claims 19–20 depend from CRM Claim 18 (only 2 dependents), leaving the CRM claims comparatively underdeveloped.
Core inventive concept: The claims address the security problem of detecting anomalous or malicious behavior in untrusted chiplets integrated into heterogeneous chiplet-based systems by deploying an AI accelerator that monitors performance-counter states of trusted chiplets, selects corrective security actions from a learned action set, and continuously refines those actions using a reinforcement learning algorithm — as recited in Claims 1, 11, and 18. The mechanism combines real-time hardware state monitoring with adaptive, reward-driven policy updates to distinguish counterfeit or compromised chiplets without relying solely on procurement-time verification.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A chiplet-based system | comprising | a first chiplet mounted to an interposer designated as from trusted sources; a second chiplet mounted to the interposer designated as not from trusted sources; an AI accelerator programmed to monitor state of the first chiplet indicating anomaly associated with second chiplet, select action from plurality of actions based on state of first chiplet, cause action to be performed, and execute reinforcement learning algorithm to update plurality of actions based on resultSearch prior art ↗ |
| Claim 11 | A method of identifying anomalies in untrusted chiplets in chiplet-based systems, the method | comprising | monitoring state of first chiplet in chiplet-based system (designated trusted), state indicating anomaly associated with second chiplet (designated untrusted); selecting action from plurality of actions based at least in part on state of first chiplet, wherein action affects operation of second chiplet; causing action to be performed by chiplet-based system; executing reinforcement learning algorithm to update plurality of actions based on result of actionSearch prior art ↗ |
| Claim 18 | One or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the one or more processors to perform operations | comprising | monitoring state of first chiplet in chiplet-based system (designated trusted), state indicating anomaly associated with second chiplet (designated untrusted); selecting action from plurality of actions based at least in part on state of first chiplet, action affects operation of second chiplet (designated untrusted); causing action to be performed; executing reinforcement learning algorithm to update plurality of actions based on resultSearch prior art ↗ |
Claim Dependency Tree
1 System: chiplet-based system with trusted first chiplet, untrusted second chiplet, AI accelerator performing RL-based anomaly monitoring and action selectionSearch Claim 1 prior art ↗
2 Adds: cryptographic processor as part of chiplet-based system also mounted to interposerSearch in Eureka ↗
3 Further: cryptographic processor implemented as chiplet separate and distinct from first chiplet, second chiplet, and AI acceleratorSearch in Eureka ↗
4 Further: causing action comprises adjusting number of encryption cycles executed by cryptographic processor for data transmitted between first and second chipletsSearch in Eureka ↗
5 Further: causing action comprises adjusting key length for encryption key used by cryptographic processor for data between first and second chipletsSearch in Eureka ↗
6 Adds: first chiplet is part of root-of-trust, second chiplet is not part of root-of-trustSearch in Eureka ↗
7 Further: data transmitted through root-of-trust is encrypted based on action performed by chiplet-based systemSearch in Eureka ↗
8 Adds: first chiplet comprises a central processing unit for the chiplet-based systemSearch in Eureka ↗
9 Adds: second chiplet comprises a memory chipletSearch in Eureka ↗
10 Adds: system further comprises SRAM with action table storing plurality of actions and weights associated with plurality of actions used to select the actionSearch in Eureka ↗
11 Method: identifying anomalies in untrusted chiplets — monitor trusted chiplet state, select action affecting untrusted chiplet, cause action, execute RL updateSearch Claim 11 prior art ↗
12 Adds: reinforcement learning algorithm comprises Q-learning algorithm or deep Q-learning algorithmSearch in Eureka ↗
13 Further: plurality of actions are stored in a Q-matrixSearch in Eureka ↗
14 Adds: state of first chiplet is represented at least in part by values stored in performance counters of the first chipletSearch in Eureka ↗
15 Further: performance counters comprise power rise, handshake signal result, resource utilization amount, cache status, processor core status, memory status, or error countSearch in Eureka ↗
16 Adds: action blocks access of second chiplet to a memory shared between first and second chipletsSearch in Eureka ↗
17 Adds: action aborts a memory transfer to/from memory shared between first and second chipletsSearch in Eureka ↗
18 CRM: non-transitory computer-readable media with instructions to monitor trusted chiplet state, select action affecting untrusted chiplet, cause action, execute RL updateSearch Claim 18 prior art ↗
19 Adds: anomaly associated with second chiplet results from second chiplet being a counterfeit chipletSearch in Eureka ↗
20 Adds: anomaly associated with second chiplet represents malicious actions taken by the second chipletSearch in Eureka ↗
| Metric | This Application | Semiconductor / Hardware Norm |
|---|---|---|
| Total claims | 20 | 15 – 25 |
| Independent claim count | 3 | 2 – 4 |
| Dependent : Independent ratio | 5.67 : 1 | 4 – 6 : 1 |
| Method claims present? | Yes — Claim 11 | Common |
| System / apparatus claims? | Yes — Claim 1 | Always |
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Drafting Quality
Drafting Quality Signals
The claim set demonstrates solid tripartite claim type coverage (system, method, CRM) and meaningful hardware anchoring through the AI accelerator limitation in Claim 1, which provides a structural §101 defense. However, the independent claims rely heavily on functional language — particularly 'monitoring a state,' 'selecting an action,' and 'executing a reinforcement learning algorithm' — without defining the structural implementation within the claim body, creating both §112 indefiniteness exposure and potential §101 vulnerability if the examiner characterizes the AI accelerator as a generic processor.
✅
Antecedent Basis
The claim set is substantially clean on antecedent basis. In Claim 1, 'the first chiplet,' 'the second chiplet,' 'the AI accelerator,' and 'the plurality of actions' all have proper antecedents introduced in the preamble or earlier claim body recitations. In Claim 11, 'the first chiplet,' 'the second chiplet,' and 'the action' are each introduced before use. Dependent Claims 4 and 5 correctly reference 'the cryptographic processor' first introduced in Claim 2. No clear antecedent basis failures are evident across the 20 claims.
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Spec–Claim Consistency
Key claim limitations map directly to specific figures and paragraphs. The 'AI accelerator' limitation in Claim 1 is supported by FIG. 3 (element 306, AI/ML Processor) and ¶[0036]–¶[0037]. The 'reinforcement learning algorithm' limitation maps to FIG. 4 (RL Block) and ¶[0038]–¶[0041]. The 'performance counters' limitation of Claim 14 is directly supported by FIG. 4 (Hardware Monitors 402) and ¶[0031]. The 'SRAM with action table' in Claim 10 maps to element 410 (SRAM for Policy/Reward) in FIG. 4 and ¶[0039]. Spec-claim consistency is strong throughout.
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Transition Word Usage
All three independent claims (1, 11, 18) correctly use 'comprising,' the broadest available transition word, leaving open the possibility that additional unclaimed elements may be present in an accused system or method. This is strategically appropriate given the multi-component chiplet architecture, where any infringer would likely have additional chiplets, peripherals, or subsystems not recited. No claim uses the narrower 'consisting of' or 'consisting essentially of,' and dependent claims correctly use 'further comprising' or 'wherein' clauses without inadvertently narrowing the scope of the independent claims.
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§112(f) Means-Plus-Function Risk
No explicit 'means for' language appears, but functional claiming in Claims 1, 11, and 18 may draw §112(f) scrutiny. Specifically, Claim 1 recites 'an artificial intelligence accelerator that is programmed to perform operations comprising' followed by purely functional steps — monitoring, selecting, causing, executing — without any structural definition of the AI accelerator's internal architecture within the claim body. While the specification at ¶[0036]–¶[0041] and FIG. 4 provides hardware detail, an examiner could challenge whether 'programmed to perform' invokes §112(f) for the accelerator as a functional unit. A stronger drafting approach would have recited at least one structural element (e.g., 'an AI accelerator comprising a master controller and an SRAM storing an action table, wherein the AI accelerator is programmed to...') within the independent claim.
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§101 Eligibility Risk
Claims 11 and 18 carry moderate Alice/Mayo exposure because they recite abstract-sounding steps — monitoring a state, selecting an action, executing a reinforcement learning algorithm — without explicitly tying these to specific hardware structural elements in the claim body. Claim 11 is a pure method claim with no explicit hardware recitation, and Claim 18's CRM framing adds a generic processor limitation that courts have repeatedly found insufficient under Step 2A of the USPTO's 2019 Eligibility Guidance. Claim 1 is the strongest §101 defense because it recites a specific physical hardware configuration (chiplets mounted to an interposer, an AI accelerator) that constitutes a 'particular machine.' Prosecution strategy should heavily rely on Claim 1's hardware tie-in and distinguish the monitoring-and-learning mechanism as an improvement to chiplet security hardware rather than an abstract data analysis method.
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Dependent Claim Fallback Quality
The dependent claims from Claim 1 add genuinely distinct technical fallbacks: Claim 2 adds the cryptographic processor element; Claim 3 narrows it to a separate chiplet; Claims 4 and 5 specify encryption cycle count and key length adjustments as action types; Claim 6 introduces the root-of-trust limitation; Claim 10 adds the SRAM action table. These are meaningfully differentiated. Under Claim 11, Claims 12–13 specify Q-learning and Q-matrix storage; Claims 14–15 add performance counter specificity; Claims 16–17 specify memory-blocking and memory-abort actions. The weakest fallbacks are Claims 19 and 20 from Claim 18, which merely restate that the anomaly results from a counterfeit or malicious chiplet without adding structural limitations — these add little prosecution value.
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Abstract Quality
An examiner reading only the abstract may not identify the reinforcement learning feedback loop as the novel contribution. The abstract accurately describes hardware components (first chiplet, second chiplet, AI accelerator, interposer) and uses the term 'reinforcement learning algorithm update' in its final sentence, but it leads with structural description and buries the adaptive, self-improving policy update mechanism — the core distinguishing feature over prior anomaly detection systems. The abstract omits any reference to performance counters, Q-matrices, or cryptographic parameter adjustment, which are key claim limitations that differentiate this invention from generic AI-based monitoring systems.
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Figure Support Quality
Figure support is comprehensive for the key structural claim limitations. The 'AI accelerator' of Claim 1 is supported by FIG. 3 (AI/ML Processor 306) and FIG. 4 (AI accelerator 406 with master controller 408). The 'SRAM with action table' of Claim 10 is shown as element 410 in FIG. 4. The 'cryptographic processor' of Claim 2 is supported by FIG. 3 (Chiplet-to-Chiplet Security 308) and FIG. 5. Performance counters of Claim 14 are shown as Hardware Monitors 402 in FIG. 4. The method steps of Claims 11 map directly to FIG. 6 flowchart steps 602–608. The only limitation without dedicated figure support is the 'root-of-trust' concept of Claim 6, which appears as a labeled boundary in FIGS. 2–3 but lacks an exploded structural diagram.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
3.5
Prosecution Defensibility
3.2
Spec–Claim Consistency
4.2
Dependent Claim Coverage
3.8
Claim Type Diversity
4.5
Figure Support Quality
4
Key observation: Claim Type Diversity scores highest (4.5/5) because the patent deliberately files system (Claim 1), method (Claim 11), and CRM (Claim 18) claims, providing enforcement optionality across hardware, software, and firmware implementations in the chiplet security space. Prosecution Defensibility scores lowest (3.2/5) because the independent claims rely on purely functional recitation of AI and RL operations without structural definition in the claim body — creating simultaneous §101 (abstract idea) and §112(f) (means-plus-function) rejection risk that a narrower but structurally-defined independent claim would have avoided. Practitioners analyzing this patent for FTO or continuation strategy should note that adding structural limitations from the specification (master controller 408, SRAM 410, hardware monitors 402) into continuation claims could substantially improve prosecution defensibility without sacrificing meaningful scope.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No structural AI hardware in independent claims CRM claim chain severely underdeveloped No procurement-stage chiplet authentication claims
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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