Patent Drafting Analysis of IBM’s Hardware for Parallel Layer-Norm Compute | US 2024/0211532 A1
Patent Drafting Analysis of IBM's Hardware for Parallel Layer-Norm Compute | US 2024/0211532 A1
A structural and strategic analysis of IBM's analog memory-based layer normalization hardware patent, examining claim architecture, drafting quality, critical gaps, and prosecution positioning across integrated circuit, system, and method claim types.
Spec Words
6,800
Across 5 sections
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Total Claims
20
3 independent · 17 dependent
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Figure Sheets
11
System architecture, circuit stages, timing diagrams, flow diagram
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Published by PatSnap Insights Team · · 12 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 62% of the estimated 6,800 total specification words, providing thorough circuit-level operational detail across paragraphs [0024]–[0077]. The claim set comprises 20 claims — 3 independent (Claims 1, 9, 17) and 17 dependent — giving a strong 5.67:1 dependent-to-independent ratio that spans integrated circuit, system, and method claim types. The 11 figure sheets provide dense timing diagrams and circuit block diagrams that map closely to the three-stage pipeline architecture described in the claims.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 11 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1 | High-level diagram of analog memory-based devices (device 114) implementing a hardware neural network, showing tiles 102, processor 110, controller 108, input lines 104, output lines 106, and readout circuits 122.Search in Eureka ↗ | System architecture |
| FIG. 2 | Details of analog memory-based device 114 implementing special-purpose digital-compute hardware for parallel layer-norm, showing VPU 210, circuit blocks 214, digital circuit 216, compute-cores 200 with tiles 102 and compute-cores (CC) 200 arranged in a grid.Search in Eureka ↗ | Key embodiment |
| FIG. 3A | Circuit diagram of Stage 1 of the layer normalization operation, showing memory device 304, FMA circuit 306, FADD circuits 308 and 310 processing input sequence 302 to produce partial sums A and B output to digital circuit 216.Search in Eureka ↗ | Claim support |
| FIG. 3B | Timing diagram of Stage 1 showing 16-cycle pipeline operation across FMA 306 and FADD circuits 308, 310 producing partial sums A1,B1 through A16,B16 with 3-cycle latencies annotated.Search in Eureka ↗ | Flow diagram |
| FIG. 4A | Stage 2 circuit diagram showing FADD circuits 402–428, multipliers 410 and 430, FMA circuits 412 and 418, and LUT 414 computing scalars C (inverse square-root of variance) and D (negation of mean times scalar C) from partial sums A and B.Search in Eureka ↗ | Claim support |
| FIG. 4B | Alternative implementation of Stage 2 with neighboring VPU1 exchange, showing FADD circuit 408 receiving intermediate sums S and S_VPU1 from a neighboring compute-core 200 to support larger input vectors (N=1024).Search in Eureka ↗ | Key embodiment |
| FIG. 4C | Timing diagram of Stage 2 showing 16-cycle accumulation pipeline for FADD circuits 402–428 producing intermediate sums S12 and T12, followed by multiplier output at cycle 30.Search in Eureka ↗ | Flow diagram |
| FIG. 4D | Continuation timing diagram of Stage 2 showing FMA 412, LUT 414, FMA 416, and FMA 418 computing scalars C and D over cycles 33–41 with 3-cycle latency stages annotated.Search in Eureka ↗ | Flow diagram |
| FIG. 5A | Stage 3 circuit diagram showing FMA circuit 502 and register 504 within circuit block 214 receiving scalars C and D from digital circuit 216 to determine output vector elements X'_k = x_k*C+D in parallel for each circuit block.Search in Eureka ↗ | Claim support |
| FIG. 5B | Timing diagram of Stage 3 showing 16-cycle operation across memory device 304 and FMA 502 producing output vector elements X'_1 through X'_64 stored in register 504.Search in Eureka ↗ | Flow diagram |
| FIG. 6 | Flow diagram of method 600 implemented by special-purpose digital-compute hardware, showing process blocks 602–616 covering receive, determine sums, determine sums of squares, determine mean, determine first scalar, determine second scalar, determine output vector, and output.Search in Eureka ↗ | Flow diagram |
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Claims
Claim Architecture Analysis
The claim set contains 3 independent claims: Claim 1 (integrated circuit apparatus), Claim 9 (system), and Claim 17 (method), providing a tripartite enforcement structure across apparatus, system, and method formats. The 17 dependent claims yield a 5.67:1 dependent-to-independent ratio, which is above the typical norm for semiconductor/AI hardware IPC classes and indicates a layered fallback strategy. Notably, Claims 1 and 9 are largely parallel in structure — a drafting choice that provides redundant enforcement paths but reduces the novelty of the dependent claim portfolio by duplicating limitations across both apparatus tracks.
Core inventive concept: The claims address the latency and throughput bottleneck of layer normalization in analog memory-based neural networks by providing a parallel pipelined circuit architecture in which each circuit block independently determines partial sums and sums of squares from time-multiplexed input sequences, a central digital circuit computes the inverse square-root scalar (C) and mean-negation scalar (D) from those partial sums, and the circuit blocks then simultaneously apply C and D to produce the normalized output vector — as recited across Claims 1, 9, and 17's 'first scalar representing an inverse square-root of a variance' and 'second scalar representing a negation of a product of the first scalar and the mean.'
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | An integrated circuit comprising: | comprising | a plurality of circuit blocks; a digital circuit; each circuit block configured to receive sequence of input data across clock cycles representing portion of input vector, determine plurality of sums and sums of squares, output to digital circuit; digital circuit configured to determine mean, first scalar (inverse square-root of variance), second scalar (negation of product of first scalar and mean), output scalars to circuit blocks; each circuit block further configured to determine output vector elements based on first scalar, second scalar, and received input sequenceSearch prior art ↗ |
| Claim 9 | A system comprising: | comprising | a first crossbar array of memory elements; a second crossbar array of memory elements; an integrated circuit including plurality of circuit blocks and a digital circuit; each circuit block configured to receive sequence of input data from first crossbar array, determine plurality of sums and sums of squares, output to digital circuit; digital circuit configured to determine mean, first scalar, second scalar, output scalars to circuit blocks; each circuit block further configured to determine output vector elements and output to second crossbar arraySearch prior art ↗ |
| Claim 17 | A method comprising: | comprising | receiving a sequence of input data across clock cycles from a first crossbar array of memory elements representing portion of input vector; determining plurality of sums and sums of squares; determining mean; determining first scalar (inverse square-root of variance); determining second scalar (negation of product of first scalar and mean); determining output vector elements based on first scalar, second scalar, and received input data; outputting output vector to second crossbar arraySearch prior art ↗ |
Claim Dependency Tree
1 Integrated circuit — plurality of circuit blocks and digital circuit performing parallel layer normalization with partial sums, variance scalar, and mean-negation scalarSearch Claim 1 prior art ↗
2 Adds: each circuit block comprises a memory device; stores and retrieves sequence of input data from memory device to determine output vector elementsSearch in Eureka ↗
3 Further: memory device is a dual-port static random-access memory (SRAM)Search in Eureka ↗
4 Adds: input vector is from first crossbar array of neural network; output vector is inputted to second crossbar array in analog memory deviceSearch in Eureka ↗
5 Further: each circuit block determines sum of corresponding input data and sum of squares of corresponding input data in parallelSearch in Eureka ↗
6 Adds: digital circuit determines first scalar by using a look-up tableSearch in Eureka ↗
7 Adds: sequence of input data at each circuit block is time-multiplexed; output vector elements outputted as another time-multiplexed sequenceSearch in Eureka ↗
8 Adds: digital circuit receives intermediate sum of squares from neighboring integrated circuit; determines first and second scalars based on plurality of sums of squares and received intermediate sum of squaresSearch in Eureka ↗
9 System — first crossbar array, second crossbar array, integrated circuit with plurality of circuit blocks and digital circuit for parallel layer normalization outputting to second crossbar arraySearch Claim 9 prior art ↗
10 Adds: each circuit block comprises a memory device; stores and retrieves sequence of input data from memory deviceSearch in Eureka ↗
11 Further: memory device is a dual-port SRAMSearch in Eureka ↗
12 Adds: first crossbar array implements first layer of neural network; second crossbar array implements first layer of neural networkSearch in Eureka ↗
13 Further: each circuit block determines sum and sum of squares of corresponding input data in parallelSearch in Eureka ↗
14 Adds: digital circuit determines first scalar by using a look-up tableSearch in Eureka ↗
15 Adds: sequence of input data at each circuit block is time-multiplexed; output data outputted as another time-multiplexed sequenceSearch in Eureka ↗
16 Adds: digital circuit receives intermediate sum of squares from neighboring integrated circuit; determines first and second scalars incorporating received intermediate sumSearch in Eureka ↗
17 Method — receiving sequence from first crossbar array, determining sums, sums of squares, mean, first scalar (inverse square-root of variance), second scalar, output vector, outputting to second crossbar arraySearch Claim 17 prior art ↗
18 Adds: storing the sequence of input data in a memory device; retrieving to determine output vector elementsSearch in Eureka ↗
19 Adds: determining sum of corresponding input data and sum of squares of corresponding input data in parallelSearch in Eureka ↗
20 Adds: determining first scalar by using a look-up tableSearch in Eureka ↗
| Metric | This Application | Semiconductor / AI Hardware Norm |
|---|---|---|
| Total claims | 20 | 15 – 25 |
| Independent claim count | 3 | 2 – 4 |
| Dependent : Independent ratio | 5.67 : 1 | 4 – 7 : 1 |
| Method claims present? | Yes — Claim 17 | Common |
| System / apparatus claims? | Yes — Claims 1, 9 | Always |
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Drafting Quality
Drafting Quality Signals
The claim set demonstrates strong hardware anchoring — the integrated circuit and system claims recite specific crossbar array memory structures, FMA/FADD circuit operations, and LUT-based inverse square-root computation, which together create a robust §101 defense and minimize abstract idea risk. However, the near-identical parallel structure of Claims 1 and 9 (integrated circuit vs. system) consumes significant claim space duplicating the same limitations, leaving dependent claims 10–16 as mirror images of Claims 2–8 with little independent fallback value.
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Antecedent Basis
Antecedent basis appears clean throughout all 20 claims. Each subsequent reference to "the digital circuit," "the plurality of circuit blocks," "the first scalar," and "the second scalar" is properly anchored to an earlier indefinite introduction in the same claim. Claims 2–8 and 10–16 each properly rely on the "plurality of circuit blocks" and "digital circuit" introduced in their parent Claims 1 and 9 respectively, and Claim 18 properly reintroduces "a memory device" to avoid antecedent issues.
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Spec–Claim Consistency
The specification provides direct, specific support for all independent claim limitations. The "plurality of circuit blocks" receiving time-multiplexed input is supported by FIG. 3A and ¶[0043]–[0044]; the "digital circuit" computing mean and inverse-square-root scalar maps directly to FIG. 4A and ¶[0048]–[0059]; the "second scalar representing a negation of a product" is explicitly derived in ¶[0059] via FMA circuit 418; and the output normalization step maps to FIG. 5A and ¶[0065]–[0068]. Every structural limitation in Claims 1, 9, and 17 has paragraph-level and figure-level specification support.
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Transition Word Usage
All independent claims (1, 9, 17) use "comprising" as the transition, which is strategically appropriate and maximally open-ended for hardware claims of this type, allowing infringers to be captured even when additional circuit components are present. No dependent claim uses a restrictive "consisting of" or "consisting essentially of" transition. The open "comprising" transition in Claim 1 appropriately does not limit the integrated circuit to only the recited circuit blocks and digital circuit, preserving breadth against design-around attempts that add supplementary logic.
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§112(f) Means-Plus-Function Risk
No "means for" or "step for" language appears anywhere in the 20 claims, eliminating the primary §112(f) trigger. Functional language does appear — e.g., "configured to receive," "configured to determine," and "configured to output" — but these are well-established non-MPF forms for hardware apparatus claims as confirmed by MPEP 2181. The specification at ¶[0079] includes a §112(f) disclaimer statement, and ¶[0027] defines "module" and "unit" with both hardware and software equivalents, providing structural disclosure that would support any borderline MPF reading under §112(f).
✅
§101 Eligibility Risk
The §101 eligibility risk is low because all three independent claims are tightly tied to specific hardware structures: Claim 1 recites an "integrated circuit" with specific circuit blocks and a digital circuit; Claim 9 recites crossbar arrays of memory elements (analog resistive memory structures); and Claim 17's method steps are all directed at physical hardware operations involving crossbar array read/write. The recitation of FMA circuits, FADD circuits, LUT hardware, and SRAM memory (Claims 3, 11, 18) in the dependent claims further grounds the invention in specific machine implementations, reducing Alice Step 2A exposure. The crossbar array memory elements (ReRAM, CBRAM, MRAM, PCM as described in ¶[0034]) are non-abstract physical structures.
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Dependent Claim Fallback Quality
A significant structural weakness is that Claims 10–16 are near-identical mirrors of Claims 2–8, simply transposing the same limitations from the integrated circuit context (Claim 1) to the system context (Claim 9) — this wastes 7 of 17 dependent claim slots without adding genuinely new fallback positions. The most valuable dependent claims are Claim 8/16 (neighboring integrated circuit intermediate sum exchange, supporting large-vector use cases), Claim 6/14 (look-up table for first scalar), and Claim 7/15 (time-multiplexed sequences), which each add distinct technical limitations. Claims 3 and 11 add SRAM specificity which is useful for design-around defense but is a well-known technology choice unlikely to survive as a meaningful distinguishing limitation.
⚠️
Abstract Quality
The abstract describes the circuit's functional outputs accurately — receive input data, determine sums and sums of squares, determine first and second scalars, determine output normalization vector — but an examiner reading only the abstract would identify the patent as covering a generic layer normalization process, not the specific parallel pipelined crossbar-array-integrated hardware architecture that constitutes the novel contribution. The abstract omits any reference to the crossbar array memory context, the multi-stage pipelining across W circuit blocks, or the LUT-based inverse square-root approximation that distinguishes this from software implementations of layer normalization.
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Figure Support Quality
Figure support is comprehensive and maps closely to all claim limitations. The three-stage pipeline architecture of Claim 1 is covered by FIG. 3A (Stage 1 partial sums and sums of squares), FIG. 4A/4B (Stage 2 digital circuit scalar computation), and FIG. 5A (Stage 3 output vector determination). The neighboring integrated circuit embodiment of Claims 8 and 16 is specifically supported by FIG. 4B showing the S_VPU1 exchange path. The LUT-based first scalar computation (Claims 6, 14, 20) is supported by FIG. 4A showing LUT 414 and FIG. 4D showing the 3-cycle LUT operation. No claim limitation lacks figure support.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
3.5
Prosecution Defensibility
4
Spec–Claim Consistency
4.5
Dependent Claim Coverage
3
Claim Type Diversity
3.5
Figure Support Quality
4.5
Key observation: Spec–Claim Consistency and Figure Support Quality share the highest scores (4.5/5.0) — every limitation in Claims 1, 9, and 17 maps directly to specific paragraphs ([0043]–[0068]) and figures (FIG. 3A through FIG. 5B), creating a prosecution record that is highly defensible against §112(a) written description challenges. The lowest score is Dependent Claim Coverage (3.0/5.0), caused by the structural decision to duplicate Claims 2–8 as Claims 10–16, consuming 7 of 17 dependent claim slots with mirror-image limitations rather than genuinely distinct technical fallback positions — a practitioner reviewing this portfolio should consider whether a continuation filing could add dependent claims targeting specific circuit component alternatives (e.g., fixed-function vs. programmable digital circuits, alternative LUT approximation methods, or GPU/FPGA implementation variants) that are disclosed in the specification but not claimed.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
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3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No CRM or firmware claim type Mirrored dependent claims waste fallback Crossbar array tie-in narrows claim scope
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US 2024/0211532 A1 — key questions answered
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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