Patent Drafting Analysis of InterDigital Patent Holdings’s Network Initiated Zero-Energy Paging Method | US 2024/0284332 A1
Patent Drafting Analysis of InterDigital Patent Holdings's Network Initiated Zero-Energy Paging Method | US 2024/0284332 A1
A structural and strategic analysis of US 2024/0284332 A1, examining claim architecture, drafting quality signals, critical gaps, and prosecution positioning for InterDigital's zero-energy on-demand paging technology.
Spec Words
18,500
Across 6 sections
Draft now ↗
Total Claims
1
1 independent · 0 dependent
Draft now ↗
Figure Sheets
56
System architecture, circuit diagrams, signal waveforms, protocol flows
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Published by PatSnap Insights Team · · 13 min read Verified by PatSnap Eureka Data
Overview
Structural Overview
The detailed description dominates at approximately 77% of total words (~14,200 of ~18,500), providing extensive technical support across 56 figure sheets covering passive receiver circuits, waveform encoding, protocol flows, and network architectures. The claim set is notably lean — only 1 independent method claim (Claim 1) with no dependent claims, yielding an extremely narrow prosecution footprint for a continuation application in this deep family. Figure coverage is exceptionally rich, spanning hardware schematics (FIGS. 11–25), signal timing diagrams (FIGS. 27–38), and network sequence diagrams (FIGS. 39–54), far exceeding what the single claim requires.
Section Word Distribution
↗ Click bars to exploreFigure Inventory — 56 Sheets
| Figure | Description | Role |
|---|---|---|
| FIG. 1A | System diagram of example communications system 100 showing WTRUs 102a-d, RAN 104, core network 106, PSTN 108, and Internet 110.Search in Eureka ↗ | System architecture |
| FIG. 1B | Block diagram of example WTRU 102 showing processor 118, transceiver 120, antenna 122, speaker/microphone 124, keypad 126, display 128, memory 130/132, power source 134, GPS chipset 136, and peripherals 138.Search in Eureka ↗ | Key embodiment |
| FIG. 1C | RAN 104 and core network 106 diagram with eNode-Bs 160a-c, MME 162, serving gateway 164, and PDN gateway 166 connected via S1 and X2 interfaces.Search in Eureka ↗ | System architecture |
| FIG. 1D | 5G NR RAN 113 and core network 115 diagram with gNBs 180a-c, AMF 182a-b, SMF 183a-b, UPF 184a-b, and DN 185a-b connected via N2, N3, N4, N6, N11 interfaces.Search in Eureka ↗ | System architecture |
| FIG. 2 | Circular diagram showing wireless connectivity approaches including WPAN/WLAN (Bluetooth, Zigbee, WiFi), Wireless WAN (2G/3G/4G), Low Power WAN (Sigfox, LoRa, NB-IoT), and other technologies.Search in Eureka ↗ | Other |
| FIG. 3 | Power vs. time diagram illustrating Power Save Mode (PSM) with dormant period, TX pulse, and paging time window.Search in Eureka ↗ | Other |
| FIG. 4 | Diagram illustrating extended DRX (eDRX) cycles showing T_eDRX, PTW intervals, legacy DRX subcycles, P_RX, P_sleep, P_deep_sleep power levels, and T_prepare timing.Search in Eureka ↗ | Claim support |
| FIG. 5 | Diagram illustrating IEEE 802.11 PSM station behavior showing doze state, data buffering, null data frame exchange, and power management bit transitions.Search in Eureka ↗ | Other |
| FIG. 6 | Timing diagram of scheduled automatic power save delivery (S-APSD) showing AP, STA wake-up, DL/UL data exchanges, acknowledgments, and service interval.Search in Eureka ↗ | Other |
| FIG. 7 | PSMP Control Header and STA Info frame format diagram showing 176-bit PSMP header, 64-bit STA Info fields including TSDID set, STA ID, DL/UL time start offsets, and durations.Search in Eureka ↗ | Other |
| FIG. 8 | Device power profile in LTE DRX showing P_TX, P_RX, P_LEAK power levels across paging cycle, transaction cycle, and network event phases (page decode, synchronization, DL setup, transmit).Search in Eureka ↗ | Claim support |
| FIG. 9A | Battery life vs. transaction cycle graph for MTC device with 12 µW leakage power showing 20-year battery life achievable with 30-hour paging cycle.Search in Eureka ↗ | Other |
| FIG. 9B | Battery life vs. transaction cycle graph for MTC device with 8 µW leakage power showing 30-year battery life achievable with 40-hour paging cycle.Search in Eureka ↗ | Other |
| FIG. 10A | Top-level architecture of facilitator showing primary TRX, CPU, and interrogator with two antennas.Search in Eureka ↗ | Key embodiment |
| FIG. 10B | Detailed interrogator architecture showing transmitter, receiver, F&TRU, carrier compensation unit (CCU), and circulator connected to a shared antenna.Search in Eureka ↗ | Key embodiment |
| FIG. 11 | Top-level radio architecture of battery-operated device showing primary active TRX, passive TRX, frequency reference unit (FRU), TRU, MCU & memory, and power management unit (PMU) with battery.Search in Eureka ↗ | Key embodiment |
| FIG. 12 | Multi-mode and multi-band device architecture with cellular TRX1 through TRXn, multi-input passive TRX, low power TRX1 through TRXm, switch and filter blocks, and CPU.Search in Eureka ↗ | Key embodiment |
| FIG. 13A | FDD device with single-band passive transceiver showing active transmitter, active receiver, passive transceiver, switch (positions a/b), duplexer, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 13B | FDD device with dual-band passive transceiver showing active transmitter, active receiver, dual-band passive transceiver, Switch 1, Switch 2, duplexer, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 14A | Half-duplex FDD device with single-band passive transceiver showing cellular transmission, cellular receiver, passive TRX, TX BPF, RX BPF, Switch 1, Switch 2, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 14B | HD-FF device with dual-band passive transceiver integrated into RF front-end showing active transmitter, active receiver, dual-band passive transceiver, Switch 2, Switch 3, TX/RX BPFs, Switch 1, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 15 | TDD mode device with single-band passive transceiver showing active transmitter, active receiver, passive TRX, TX BPF, RX BPF, Switch 1, Switch 2, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 16A | Dual-band FDD device with multi-input passive TRX integrated into two receive paths using Band 1 and Band 2 duplexers, Switch 1 through Switch 3, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 16B | Single-band FDD device with dual-band downlink carrier aggregation using Band 1 duplexer, Band 2 filter, multi-input passive TRX, Switch 1, Switch 2, and processor.Search in Eureka ↗ | Key embodiment |
| FIG. 17 | Radio-triggered wakeup receiver architecture (P-RX) showing passive front-end with parameters {n,ζ}, stored energy thresholding A-to-I converter with thresholds {V_TH1..V_THk}, and command interpreter producing output Y.Search in Eureka ↗ | Claim support |
| FIG. 18A | Single-ended passive front-end schematic showing transformer T1 (1:n turns ratio), diode D1, resistor R1, and storage capacitor C_SUPP producing V_FE output.Search in Eureka ↗ | Claim support |
| FIG. 18B | Differential/balanced passive front-end schematic with transformer T1 (1:n), diodes D1/D2, resistors R1/R2, and capacitor C_SUPP for balanced rectification of r(t) input.Search in Eureka ↗ | Claim support |
| FIG. 19A | Output waveform V_FE vs. time for continuously persistent sinusoidal input r(t) showing C_SUPP1 vs. C_SUPP2 charging curves reaching threshold V_TH at times t_TH1 and t_TH2.Search in Eureka ↗ | Claim support |
| FIG. 19B | Passive front-end V_FE output response to pulsed sinusoidal input showing capacitor C_SUPP1 voltage charging and threshold crossing at t_TH1.Search in Eureka ↗ | Claim support |
| FIG. 20A | Analog-to-information (A-to-I) converter circuit with storage capacitor C_SUPP, shunting switch S2, and comparator with threshold V_TH producing pulse output P.Search in Eureka ↗ | Claim support |
| FIG. 20B | A-to-I converter input/output waveforms showing V_FE charging with hysteresis band, threshold V_TH crossings, and resulting pulse train output P.Search in Eureka ↗ | Claim support |
| FIG. 21 | A-to-I converter circuit with automatic sensitivity control using comparator, resistors R1/R2/R3, V_REF reference, switch S2, and storage capacitor C_SUPP.Search in Eureka ↗ | Claim support |
| FIG. 22A | Single-ended A-to-I implementation with primary storage C_SUPP, supplementary storage C_PRIM, switch S1, switch S2, and comparator with V_TH producing output P.Search in Eureka ↗ | Claim support |
| FIG. 22B | Fully differential balanced A-to-I implementation with switches S1-S4, capacitors C_SUPP and C_PRIM, and comparator producing P and /P outputs.Search in Eureka ↗ | Claim support |
| FIG. 23 | Alternative A-to-I converter with k comparators each having distinct thresholds V_TH1 through V_THk sharing V_FE input from C_SUPP, producing outputs P1 through Pk.Search in Eureka ↗ | Claim support |
| FIG. 24 | Complete passive receiver schematic showing k-input passive front-end array (with transformer T1, diode D1, resistor R1, capacitor C1), A-to-I array, and command interpreter with threshold V_TH1.Search in Eureka ↗ | Claim support |
| FIG. 25 | Passive transceiver (P-TRX) architecture with MUX, passive receiver, load bank, load modulation waveform generation, CU & D/A, and F&TRU blocks.Search in Eureka ↗ | Key embodiment |
| FIG. 26A | Single-input stored energy thresholding event counting wakeup command interpreter (ET-CI) with counter C[m:0] and combinatorial logic block producing output Y.Search in Eureka ↗ | Claim support |
| FIG. 26B | Multi-input ET-CI for multi-input device with three inputs P1/P2/P3, counter C[m:0], combinatorial logic, and programmable parameters {N1,N2,...Nk}.Search in Eureka ↗ | Claim support |
| FIG. 27A | Single-input ET-CI operation showing signal r(t), V_FE voltage with hysteresis and V_TH threshold, pulse output P, and command interpreter output Y for two threshold events.Search in Eureka ↗ | Claim support |
| FIG. 27B | Single-input ET-CI configured for three threshold events showing r(t), V_FE, P pulse train (N=3 pulses), and Y output interrupt.Search in Eureka ↗ | Claim support |
| FIG. 28A | Pulse separation decoding (PSD) data detector with CLK input, counter C[m:0] with /RST, D-Q latch, and data detector with parameters C0, C1 producing output X.Search in Eureka ↗ | Claim support |
| FIG. 28B | Single input ETESD-CI with pulse separation decoding data detector, CLK input, decision logic with parameter N, and output Y.Search in Eureka ↗ | Claim support |
| FIG. 28C | Three-input ETESD-CI with three pulse separation decoding data detectors (P1/P2/P3 inputs), CLK, decision logic with {N1,N2,N3} parameters, and output Y.Search in Eureka ↗ | Claim support |
| FIG. 29 | Single-input energy threshold event separation decoding command interpreter theory of operation showing r(t), V_FE with hysteresis, P pulses with start sequence, X decoded data bits (0/1), and Y interrupt output.Search in Eureka ↗ | Claim support |
| FIG. 30 | Resource cube diagram for wakeup word construction with three dimensions: frequency (f1 to fk), time (t1 to tL), and angle (θ1), showing how resources combine to form wakeup signal sequences.Search in Eureka ↗ | Key embodiment |
| FIG. 31 | Transmitter structure for wakeup command generation showing User-1 through User-n bits, wakeup command bits, FEC, modulation, modulation generator, S/P, IFFT, P/S, D/A, and upconversion mixer.Search in Eureka ↗ | Key embodiment |
| FIG. 32A | Symbolic representation of a 3/9th-strength f1 wakeup word showing time slots t1-tL with active slots at t6 and t7 on frequency f1.Search in Eureka ↗ | Claim support |
| FIG. 32B | A (1, f1) wakeup word using single frequency f1 and L=9 time resources with multiple active time slots (t1-t9).Search in Eureka ↗ | Claim support |
| FIG. 32C | Wakeup words utilizing single frequency resource with up to L time resources showing time-domain sinusoidal representation of a weak signal.Search in Eureka ↗ | Claim support |
| FIG. 32D | A (1, f1) wakeup word time-domain sinusoidal representation showing a fully dense signal waveform.Search in Eureka ↗ | Claim support |
| FIG. 33A | Alternative implementation of a (3/9, f1) wakeup word showing time-frequency grid for f1 with active slots at t2, t6, t8, and their corresponding time-domain sinusoidal bursts.Search in Eureka ↗ | Claim support |
| FIG. 33B | Another alternative implementation of (3/9, f1) wakeup word showing time-frequency grid with active slots t1, t2, t3 at f2 and their corresponding time-domain sinusoidal bursts.Search in Eureka ↗ | Claim support |
| FIG. 34A | Wakeup word employing (3/9, f1) and (1, fk) frequency-time combination showing resource allocation across f1 and fk frequencies.Search in Eureka ↗ | Claim support |
| FIG. 34B | A {(3/9, f1), (4/9, f2), (1, fk)} wakeup word showing active time-frequency resources across f1, f2, and fk channels.Search in Eureka ↗ | Claim support |
| FIG. 35A | Multi-angle wakeup word employing identical (3/9, f1) and (1, f2) resource combinations on two angle resources θ1 and θ2 in overlapping resource frame.Search in Eureka ↗ | Claim support |
| FIG. 35B | Multi-angle, multi-frequency wakeup word [{θ1,(3/5,f1)},{θ2,(4/9,f1),(1,f2)}] showing separate angle resource frames θ1 and θ2 with different time-frequency patterns.Search in Eureka ↗ | Claim support |
| FIG. 36A | 4-word (N=4) wakeup command with single angle (m=1), single frequency (k=1), and L=5 time resources per word, a (4,1,1,5) command structure.Search in Eureka ↗ | Claim support |
| FIG. 36B | Stored-energy threshold event stacking wakeup command (3,1,2,9): N=3 words, m=1 angle, k=2 frequencies (f1 and f2), L=9 time resources per word.Search in Eureka ↗ | Claim support |
| FIG. 37A | First quantization level of a stored-energy quantization wakeup word employing single angle, single frequency f1, and 8 time resources with one active slot at t5.Search in Eureka ↗ | Claim support |
| FIG. 37B | Second quantization level wakeup word with single angle, single f1, 8 time resources, with two active time slots.Search in Eureka ↗ | Claim support |
| FIG. 37C | Third quantization level wakeup word with single angle, single frequency, 8 time resources, and multiple active slots indicating higher energy level.Search in Eureka ↗ | Claim support |
| FIG. 37D | Fourth (maximum) quantization level wakeup word with all 8 time resources active at single angle and frequency, representing full strength signal.Search in Eureka ↗ | Claim support |
| FIG. 38 | Constant-energy amplitude modulation waveform showing start sequence followed by sinusoids of amplitudes A0 and A1 with durations T0 and T1 encoding binary bits 0 and 1.Search in Eureka ↗ | Claim support |
| FIG. 39 | End-to-end network-initiated on-demand zero-energy paging system with asset management entity, asset database, core network & internet, eNodeB1/eNodeB2/eNodeB3, facilitator, and device connected via Uu, PC5, and zero-energy interfaces.Search in Eureka ↗ | System architecture |
| FIG. 40 | On-demand zero-energy paging procedure sequence diagram showing 10 steps between AME/Network, eNB1, facilitator, eNB2, eNB3, and device, including sleep mode placement, wakeup command transmission, and active TX activation.Search in Eureka ↗ | Flow diagram |
| FIG. 41A | eNodeB and facilitator signal power levels diagram showing P_eNB1_TX, P_eNB2_TX, P_eNB3_TX, P_Facilitator, and P_eNB1_RX power levels during network event and signal phases 5-10.Search in Eureka ↗ | Claim support |
| FIG. 41B | Device power profile showing P_TX, P_RX, P_LEAK levels and latency between network event and device reception of step 10 response.Search in Eureka ↗ | Claim support |
| FIG. 42 | Hybrid paging cycle adaptation procedure showing 9 steps between AME/Network, eNB1, eNB2, eNB3, and device, with DRX cycle configuration, over-the-air interrupt, duty cycle period changes, and active TRX activation.Search in Eureka ↗ | Flow diagram |
| FIG. 43A | eNodeB power profile and signals during hybrid paging procedure showing P_eNB1_TX, P_eNB2_TX, P_eNB3_TX transmit levels for over-the-air interrupt signals 4-8 and RX step.Search in Eureka ↗ | Claim support |
| FIG. 43B | Device power profiles for hybrid paging showing P_TX, P_RX, P_LEAK during long paging cycle, network event, short paging cycle transitions, and steps 9-RX.Search in Eureka ↗ | Claim support |
| FIG. 44 | Detailed on-demand zero-energy wakeup procedure diagram showing eNodeB, device circuitry (passive receiver with diode D1, resistor R1, capacitor C1, comparator, wakeup command interpreter, PMU, primary TRX), and critical signal waveforms V_FE, P, Y, WU.Search in Eureka ↗ | Claim support |
| FIG. 45 | Backscattered and modulated carrier diagram showing wakeup receiver input sinusoid, backscattered carrier, VCO activation PN sequence generation start, and back-scattered modulated carrier waveforms.Search in Eureka ↗ | Key embodiment |
| FIG. 46 | PN sequence detection procedure showing PN sequences of period T, matched filter, I²+q² power computation, T delay integrator, Max/Index selector, and threshold comparison H0/H1.Search in Eureka ↗ | Key embodiment |
| FIG. 47 | Frequency offset estimator showing matched filter, sample extractor with max index output providing A1exp(jθ1) and A2exp(jθ2) samples, and frequency error estimation formula k*(θ1-θ2)/T.Search in Eureka ↗ | Key embodiment |
| FIG. 48 | Cell cluster deployment diagram showing tracking areas A, B, C with cell groupings (Cell A1-A7, B1-B9, C1-C5) and device trajectory crossing TA boundaries (A-B) and (B-C).Search in Eureka ↗ | Other |
| FIG. 49 | WTRU-initiated wakeup command energy signature assignment procedure showing WTRU-1, WTRU-2, and eNB sequence with system information message, random access, RRC connection request/setup/reject exchanges using signatures e1 and e2.Search in Eureka ↗ | Flow diagram |
| FIG. 50 | Adaptive power transmission flow diagram for wakeup process showing start, set estimated power P and x=0, transmit with power P, check wakeup confirmation, increment x and increase P by δ(x)·r on failure, stop on success.Search in Eureka ↗ | Flow diagram |
| FIG. 51 | Resource block (RB) usage information sharing procedure with primary eNB, eNB1, eNB2, and WTRU/sensor showing additive power estimation steps and paging instant T2 delivery.Search in Eureka ↗ | Flow diagram |
| FIG. 52 | Specialized beacon transmission diagram showing WiFi OFDM symbol (4us) with wake-up pilot subcarriers (specialized beacon indicator), wake-up signature subcarriers, and wake-up signature subcarrier allocation across frequency and time.Search in Eureka ↗ | Key embodiment |
| FIG. 53 | Dedicated wakeup signal transmission showing beacon timeline, medium busy period, dedicated wake-up signal OFDM symbols with wake-up frame indicator and wake-up signature subcarriers.Search in Eureka ↗ | Key embodiment |
| FIG. 54 | Call flow for wakeup command energy signature configuration, STA wakeup, and data transfer showing AP, STA-1, STA-2 exchanging null frames, secondary wakeup RX signature config, secondary wake-up signals, PS-POLL, and data transfer.Search in Eureka ↗ | Flow diagram |
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Claims
Claim Architecture Analysis
The application contains exactly 1 independent claim — a method claim (Claim 1) — with zero dependent claims, yielding a 0:1 dependent-to-independent ratio that is dramatically below the telecom/wireless industry norm of 15–20 dependent claims per independent. This extremely sparse claim architecture in a continuation filing (of US 11,956,725 and US 11,470,553) suggests the applicant may be pursuing a narrow, focused prosecution target rather than broad portfolio coverage. The sole claim combines first and second transceiver DRX cycle management with energy signature decoding — a highly specific method recitation that creates substantial prosecution risk if any limitation is found in prior art.
Core inventive concept: Claim 1 addresses the fundamental energy-latency tradeoff in IoT device paging by enabling a network-initiated wakeup without requiring the WTRU's primary transceiver to remain active — the method requires a first transceiver to receive DRX configuration and a second transceiver to receive a first message with an energy signature comprising "one or more sections of different time duration and amplitudes with a same energy," which upon decoding determines a second DRX cycle and activates the first transceiver for data reception.
Independent Claim Dissection
| Claim | Preamble | Transition | Key Body Elements |
|---|---|---|---|
| Claim 1 | A method implemented by a wireless transmit/receive unit (WTRU) comprising a first transceiver and a second transceiver | comprising | receiving first configuration information for first DRX cycle using first transceiver; entering first DRX cycle based on configuration; receiving first message from first network node via second transceiver comprising command to interrupt first DRX cycle with second DRX cycle configuration, priority level, and energy signature with same-energy sections of different time/amplitude; determining second DRX cycle for first transceiver; activating first transceiver and receiving second messageSearch prior art ↗ |
Claim Dependency Tree
1 Method for WTRU with first and second transceiver: receive DRX config, enter first DRX cycle, receive energy-signature-encoded network interrupt via second transceiver, determine second DRX cycle, activate first transceiverSearch Claim 1 prior art ↗
| Metric | This Application | Wireless / Telecom Industry Norm |
|---|---|---|
| Total claims | 1 | 15 – 25 |
| Independent claim count | 1 | 3 – 5 |
| Dependent : Independent ratio | 0.00 : 1 | 4 – 8 : 1 |
| Method claims present? | Yes — Claim 1 | Always present |
| System / apparatus claims? | No | Common (apparatus + method pairing) |
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Drafting Quality
Drafting Quality Signals
The specification is technically comprehensive with 56 figures providing granular circuit-level and protocol-level support for every disclosed embodiment, giving examiners and litigators an unusually deep written description to work from. However, the strategic drafting quality is critically undermined by the presence of only a single method claim with no dependent fallbacks and no apparatus or CRM claims, leaving InterDigital with virtually no claim-family resilience if Claim 1 faces a rejection or is challenged post-grant.
✅
Antecedent Basis
The single claim is internally consistent with no antecedent basis violations — "the first transceiver," "the second transceiver," "the first DRX cycle," "the second DRX cycle," "the first message," and "the second message" all have clean antecedents introduced in earlier limitations. The preamble introduces "a first transceiver and a second transceiver," and each subsequent use of "the first transceiver" and "the second transceiver" refers back unambiguously. With only one claim, antecedent basis review is limited but passes cleanly.
✅
Spec–Claim Consistency
Every limitation in Claim 1 maps precisely to specification sections and figures. The first transceiver / second transceiver dual-TRX architecture is directly supported by FIG. 11 and §§[0169]–[0170]. The DRX cycle configuration receiving step maps to FIG. 42 (step 1) and §[0234]. The energy signature limitation — "one or more sections of different time duration and amplitudes with a same energy" — maps to FIG. 38, FIG. 44, and §§[0215]–[0216]. The second DRX determination and first transceiver activation maps to FIG. 42 steps 7–8 and FIG. 43B. Specification support is exceptionally well-aligned.
✅
Transition Word Usage
Claim 1 uses "comprising" as the transition, which is the broadest available choice and appropriate for an apparatus/method claim in this telecommunications art unit. "Comprising" means the claim does not exclude additional steps or elements, so a WTRU performing the recited steps plus additional non-recited steps would still infringe. No missed opportunity arises from the transition choice itself; the strategic gap lies in the absence of alternative claim types, not transition selection.
✅
§112(f) Means-Plus-Function Risk
Claim 1 contains no "means for" or "step for" language, and no nonce-word functional labels (such as "mechanism for" or "module for") that would trigger §112(f) interpretation. The claim recites method steps using active verbs ("receiving," "entering," "determining," "activating") which are method-step format and not susceptible to §112(f) means-plus-function treatment. The energy signature is defined structurally — "comprising one or more sections of different time duration and amplitudes with a same energy" — providing sufficient structural definition to avoid §112 indefiniteness challenges.
⚠️
§101 Eligibility Risk
The Alice exposure for Claim 1 is moderate but manageable because the claim is a WTRU method requiring physical transceiver operation (receiving signals, activating hardware), which provides a hardware tie-in under step 2A prong 1. However, the critical "determining the second DRX cycle" step is functional and could be characterized as an abstract idea (a mathematical relationship or logical decision process) without the saving grace of physical activation. The hardware anchor — "activating the first transceiver and receiving a second message" — is the §101 defense, but an examiner could argue the determination step dominates. The absence of apparatus claims means no alternative §101 framing as a "machine" is available.
⚠️
Dependent Claim Fallback Quality
This application has zero dependent claims, which is the most significant drafting vulnerability in the entire prosecution file. If the examiner rejects Claim 1 on §102 or §103 grounds, the applicant has no narrower fallback positions available without filing a claim amendment, which requires examiner approval. The specification supports dozens of distinct fallback limitations that were not claimed: specific energy signature types (SEQ, SET, SETES), specific passive receiver circuit configurations (C_SUPP values, comparator hysteresis), priority-level-based DRX determination, specific paging cycle ranges, and backscattering confirmation procedures. All of these are unexploited fallback opportunities.
⚠️
Abstract Quality
The abstract accurately describes the WTRU hardware configuration (one or more antennas, first transceiver, second transceiver) and key functional behaviors (receiving a first signal using zero energy, extracting energy, examining energy threshold events, decoding an energy signature, activating a second transceiver). However, the abstract does not mention the DRX cycle configuration or interruption mechanism that defines Claim 1's novel contribution — a reader of only the abstract would not identify the specific DRX-interrupt-via-energy-signature mechanism claimed. This divergence between abstract content and claim content could mislead an examiner's initial prior art search.
✅
Figure Support Quality
Figure support is exceptional across all claim limitations. The dual-transceiver structure maps to FIG. 11 and FIG. 44. The DRX cycle configuration and interruption maps to FIGS. 42–43B. The energy signature with same-energy sections of differing amplitude/duration maps to FIG. 38 (constant-energy AM waveform, §[0215]–[0216]) and FIG. 44 (critical signals diagram). The second DRX cycle determination and first transceiver activation maps to FIG. 42 steps 7–9 and FIG. 43B. The only potential gap is that no single figure shows the complete flow of Claim 1 step-by-step from DRX configuration receipt through second message reception, though FIG. 42 comes closest.
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Scorecard
Strategic Intent Scorecard
Multi-dimensional assessment of this application's patent strategy quality, based on claim structure, specification depth, and prosecution positioning.
Claim Breadth
2.5
Prosecution Defensibility
1.5
Spec–Claim Consistency
4.8
Dependent Claim Coverage
0.5
Claim Type Diversity
1
Figure Support Quality
4.7
Key observation: Spec–Claim Consistency scores highest (4.8/5) because 56 figures and 230+ paragraphs provide meticulous support for every element of Claim 1, ensuring written description and enablement defenses are among the strongest in this art unit. Dependent Claim Coverage scores lowest (0.5/5) because the application has literally zero dependent claims — a critical structural weakness for a continuation filing that leaves no fallback if Claim 1 is rejected or later challenged during IPR. Practitioners should immediately prepare a continuation with 15–20 dependent claims drawn to the disclosed SEQ, SET, SETES encoding methods, specific circuit configurations (C_SUPP, comparator hysteresis), and apparatus/CRM claim types before this application issues.
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Critical Gaps
3 Critical Gaps in This Claim Set
A senior-attorney lens on the three highest-priority structural weaknesses — what each exposes in prosecution and litigation, and what a stronger filing would have done differently.
🔒
3 Critical Gaps in This Claim Set
See the full attorney-level analysis of what this application leaves unprotected — and how to draft it more defensively for your own filings.
No apparatus or CRM claims filed Zero dependent claims as fallback SEQ/SET/SETES encoding unclaimed
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Disclaimer: This analysis is generated by PatSnap Eureka AI based on publicly available patent data from the USPTO. It does not constitute legal advice and should not be relied upon as such. Patent data may be subject to change as prosecution progresses. Scores and assessments reflect automated analysis and may not capture all relevant legal or technical nuances. Always consult a qualified patent attorney for formal legal opinions on patentability, freedom to operate, or infringement.
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